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mos integrated circuit pd70f3107a, 70f3107a(a) v850e/ma1 tm 32-bit single-chip microcontrollers document no. u15846ej1v0ds00 (1st edition) date published january 2002 n cp(k) printed in japan data sheet ? 2002 description the pd70f3107a and 70f3107a(a) are products of the v850 series tm of 32-bit single-chip microcontrollers for real-time control applications. this microcontroller integrates a 32-bit cpu, rom, ram, an interrupt controller, a real-time pulse unit, a serial interface, an a/d converter, a dma controller, and other functions on a single chip. the pd70f3107a and 70f3107a(a) are products that substitute flash memory for the internal mask rom of the pd703107a and 703107a(a). this enables users to perform on-board program writing and erasure, making this product effective for evaluation during system development, small-lot production of multiple devices, and rapid production start. detailed function descriptions are provided in the following user?s manuals. be sure to read them before designing. v850e/ma1 hardware user?s manual: u14359e v850e1 architecture user?s manual: u14559e features { number of instructions: 83 { minimum instruction execution time: 20 ns (50 mhz internal operation) { general-purpose registers: 32 bits 32 registers { instruction set optimized for control applications { internal memory flash memory: 256 kb ram: 10 kb { memory access control (supporting edo dram, sdram, and page rom) { advanced internal interrupt controller { real-time pulse unit suitable for control operations { powerful serial interface (with dedicated internal baud rate generator) { on-chip clock generator { 10-bit resolution a/d converter: 8 channels { dma controller: 4 channels { power saving functions { can be replaced with mask rom-incorporated pd703105a, 703106a, 703106a(a), 703107a, or 703107a(a) for mass production applications { office machines (such as ink jet printers, facsimiles, and ppcs) { multimedia systems (such as digital still cameras, dvd players, and video printers) the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
data sheet u15846ej1v0ds 2 pd70f3107a, 70f3107a(a) ordering information part number package quality grade pd70f3107agj-uen 144-pin plastic lqfp (fine pitch) (20 20) standard pd70f3107af1-en4 161-pin plastic fbga (13 13) standard pd70f3107agj(a)-uen 144-pin plastic lqfp (fine pitch) (20 20) special the pd70f3107a and pd70f3107a(a) differ in the quality grade only. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
data sheet u15846ej1v0ds 3 pd70f3107a, 70f3107a(a) pin configuration (top view) ? ? ? ? 144-pin plastic lqfp (fine pitch) (20 20) pd70f3107agj-uen pd70f3107agj(a)-uen d14/pdl14 d13/pdl13 d12/pdl12 d11/pdl11 d10/pdl10 d9/pdl9 d8/pdl8 v dd v ss d7/pdl7 d6/pdl6 d5/pdl5 d4/pdl4 d3/pdl3 d2/pdl2 d1/pdl1 d0/pdl0 v pp /mode2 dmarq3/intp103/p07 dmarq2/intp102/p06 dmarq1/intp101/p05 dmarq0/intp100/p04 to00/p03 intp001/p02 ti000/intp000/p01 pwm0/p00 v dd v ss dmaak3/pbd3 dmaak2/pbd2 dmaak1/pbd1 dmaak0/pbd0 to01/p13 intp011/p12 ti010/intp010/p11 pwm1/p10 pcd3/ube/sdras pcs0/cs0 pcs1/cs1/ras1 pcs2/cs2/iowr pcs3/cs3/ras3 pcs4/cs4/ras4 pcs5/cs5/iord pcs6/cs6/ras6 pcs7/cs7 v ss v dd pct0/lcas/lwr/ldqm pct1/ucas/uwr/udqm pct4/rd pct5/we pct6/oe pct7/bcyst pcm0/wait pcm1/clkout/busclk pcm2/hldak pcm3/hldrq pcm4/refrq pcm5/selfref p50/intp030/ti030 p51/intp031 p52/to03 v ss v dd p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 v dd v ss tc3/intp113/p27 tc2/intp112/p26 tc1/intp111/p25 tc0/intp110/p24 to02/p23 intp021/p22 ti020/intp020/p21 nmi/p20 v dd v ss adtrg/intp123/p37 intp122/p36 intp121/p35 rxd2/intp120/p34 txd2/intp133/p33 sck2/intp132/p32 si2/intp131/p31 so2/intp130/p30 mode1 mode0 reset cksel cv dd x2 x1 cv ss sck1/p45 rxd1/si1/p44 txd1/so1/p43 sck0/p42 rxd0/si0/p41 txd0/so0/p40 av dd /av ref av ss pdl15/d15 pal0/a0 pal1/a1 pal2/a2 pal3/a3 pal4/a4 pal5/a5 pal6/a6 pal7/a7 v ss v dd pal8/a8 pal9/a9 pal10/a10 pal11/a11 pal12/a12 pal13/a13 pal14/a14 pal15/a15 v ss v dd pah0/a16 pah1/a17 pah2/a18 pah3/a19 pah4/a20 pah5/a21 pah6/a22 pah7/a23 pah8/a24 pah9/a25 v ss v dd pcd0/sdcke pcd1/sdclk pcd2/lbe/sdcas 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
data sheet u15846ej1v0ds 4 pd70f3107a, 70f3107a(a) ? 161-pin plastic fbga (13 13) pd70f3107af1-en4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 top view bottom view pnmlk jhgfedcba abcdefghj klmnp index mark index mark (1/2) pin no. pin name pin no. pin name pin no. pin name a1 ? b10 a21/pah5 d5 a6/pal6 a2 d15/pdl15 b11 a25/pah9 d6 a10/pal10 a3 a2/pal2 b12 sdclk/pcd1 d7 a14/pal14 a4 a5/pal5 b13 cs1/ras1/pcs1 d8 a16/pah0 a5 ? b14 ? d9 a20/pah4 a6 a9/pal9 c1 ? d10 a23/pah7 a7 a12/pal12 c2 d9/pdl9 d11 sdcke/pcd0 a8 a15/pal15 c3 d13/pdl13 d12 cs0/pcs0 a9 a17/pah1 c4 a1/pal1 d13 cs5/iord/pcs5 a10 ? c5 a7/pal7 d14 ? a11 a24/pah8 c6 v dd e1 d5/pdl5 a12 v dd c7 a11/pal11 e2 d7/pdl7 a13 lbe/sdcas/pcd2 c8 v dd e3 d8/pdl8 a14 ube/sdras/pcd3 c9 a19/pah3 e4 d11/pdl11 b1 ? c10 a22/pah6 e5 ? b2 d12/pdl12 c11 v ss e11 cs6/ras6/pcs6 b3 a0/pal0 c12 cs3/ras3/pcs3 e12 cs4/ras4/pcs4 b4 a4/pal4 c13 cs2/iowr/pcs2 e13 cs7/pcs7 b5 v ss c14 ? e14 v ss b6 a8/pal8 d1 v ss f1 d2/pdl2 b7 a13/pal13 d2 d10/pdl10 f2 d3/pdl3 b8 v ss d3 d14/pdl14 f3 d4/pdl4 b9 a18/pah2 d4 a3/pal3 f4 v dd
data sheet u15846ej1v0ds 5 pd70f3107a, 70f3107a(a) (2/2) pin no. pin name pin no. pin name pin no. pin name f11 rd/pct4 l6 v dd p5 ? f12 v dd l7 intp122/p36 p6 intp121/p35 f13 lcas/lwr/ldqm/pct0 l8 si2/intp131/p31 p7 sck2/intp132/p32 f14 ucas/uwr/udqm/pct1 l9 reset p8 mode1 g1 v pp /mode2 l10 txd1/so1/p43 p9 cv dd g2 dmarq3/intp103/p07 l11 ani7/p77 p10 x1 g3 d0/pdl0 l12 ani4/p74 p11 ? g4 d6/pdl6 l13 ani3/p73 p12 rxd1/si1/p44 g11 wait/pcm0 l14 ani2/p72 p13 rxd0/si0/p41 g12 we/pct5 m1 ? p14 ? g13 bcyst/pct7 m2 intp011/p12 g14 oe/pct6 m3 to01/p13 h1 dmarq2/intp102/p06 m4 tc2/intp112/p26 h2 dmarq1/intp101/p05 m5 ti020/intp020/p21 h3 dmarq0/intp100/p04 m6 v ss h4 d1/pdl1 m7 rxd2/intp120/p34 h11 refrq/pcm4 m8 mode0 h12 hldrq/pcm3 m9 cksel h13 hldak/pcm2 m10 sck1/p45 h14 clkout/busclk/pcm1 m11 txd0/so0/p40 j1 to00/p03 m12 ani6/p76 j2 ti000/intp000/p01 m13 ani5/p75 j3 v dd m14 ? j4 intp001/p02 n1 ? j11 to03/p52 n2 pwm1/p10 j12 ti030/intp030/p50 n3 tc3/intp113/p27 j13 selfref/pcm5 n4 tc0/intp110/p24 j14 intp031/p51 n5 nmi/p20 k1 pwm0/p00 n6 adtrg/intp123/p37 k2 v ss n7 txd2/intp133/p33 k3 dmaak1/pbd1 n8 so2/intp130/p30 k4 dmaak3/pbd3 n9 x2 k11 ani1/p71 n10 cv ss k12 ani0/p70 n11 sck0/p42 k13 v ss n12 av dd /av ref k14 v dd n13 av ss l1 ? n14 ? l2 dmaak2/pbd2 p1 v dd l3 ti010/intp010/p11 p2 v ss l4 dmaak0/pbd0 p3 tc1/intp111/p25 l5 to02/p23 p4 intp021/p22 remark leave the a1, a5, a10, b1, b14, c1, c14, d14, e5, l1, m1, m14, n1, n14, p5, p11, and p14 pins open.
data sheet u15846ej1v0ds 6 pd70f3107a, 70f3107a(a) pin identification a0 to a25: address bus p70 to p77: port 7 adtrg: a/d trigger input pah0 to pah9: port ah ani0 to ani7: analog input pal0 to pal15: port al av dd : analog power supply pbd0 to pbd3: port bd av ref : analog reference voltage pcd0 to pcd3: port cd av ss : analog ground pcm0 to pcm5: port cm bcyst: bus cycle start timing pcs0 to pcs7: port cs busclk: bus clock output pct0, pct1, cksel: clock generator operating mode select pct4 to pct7: port ct clkout: clock output pdl0 to pdl15: port dl cs0 to cs7: chip select pwm0, pwm1: pulse width modulation cv dd : clock generator power supply ras1, ras3, cv ss : clock generator ground ras4, ras6: row address strobe d0 to d15: data bus rd: read dmaak0 to dmaak3: dma acknowledge refrq: refresh request dmarq0 to dmarq3: dma request reset: reset hldak: hold acknowledge rxd0 to rxd2: receive data hldrq: hold request sck0 to sck2: serial clock intp000, intp001, sdcas: sdram column address strobe intp010, intp011, sdcke: sdram clock enable intp020, intp021, sdclk: sdram clock output intp030, intp031, sdras: sdram row address strobe intp100 to intp103, selfref: self-refresh request intp110 to intp113, si0 to si2: serial input intp120 to intp123, so0 to so2: serial output intp130 to intp133: interrupt request from peripherals tc0 to tc3: terminal count signal iord: i/o read strobe ti000, ti010, iowr: i/o write strobe ti020, ti030: timer input lbe: lower byte enable to00 to to03: timer output lcas: lower column address strobe txd0 to txd2: transmit data ldqm: lower dq mask enable ube: upper byte enable lwr: lower write strobe ucas: upper column address strobe mode0 to mode2: mode udqm: upper dq mask enable nmi: non-maskable interrupt request uwr: upper write strobe oe: output enable v dd : power supply p00 to p07: port 0 v pp : programming power supply p10 to p13: port 1 v ss : ground p20 to p27: port 2 wait: wait p30 to p37: port 3 we: write enable p40 to p45: port 4 x1, x2: crystal p50 to p52: port 5
data sheet u15846ej1v0ds 7 pd70f3107a, 70f3107a(a) internal block diagram nmi intp000 to intp001, intp010 to intp011, intp020 to intp021, intp030 to intp031 intp100 to intp103, intp110 to intp113, intp120 to intp123, intp130 to intp133 to00 to to03 ti000, ti010, ti020, ti030 intc flash memory rpu sio 256 kb 10 kb ram cpu 32-bit barrel shifter pc system registers general- purpose registers (32 bits 32) alu multiplier (32 32 64) ports pdl0 to pdl15 pal0 to pal15 pah0 to pah9 pcs0 to pcs7 pct0, pct1, pct4 to pct7 pcm0 to pcm5 pcd0 to pcd3 pbd0 to pbd3 p70 to p77 p50 to p52 p40 to p45 p30 to p37 p21 to p27 p20 p10 to p13 p00 to p07 cg system controller bcu clkout cksel x1 x2 cv dd cv ss mode0, mode1 mode2/v pp reset v dd v ss uart0/csi0 uart1/csi1 uart2 csi2 adc so0/txd0 si0/rxd0 sck0 so1/txd1 si1/rxd1 sck1 txd2 rxd2 pwm0 so2 si2 sck2 ani0 to ani7 av ref /av dd av ss adtrg instruction queue memc hldrq hldak cs0, cs7 cs1/ras1, cs3/ras3 cs4/ras4, cs6/ras6 cs2/iord cs5/iowr selfref refrq bcyst lbe/sdcas ube/sdras sdclk sdcke we rd oe uwr/ucas/udqm lwr/lcas/ldqm wait a0 to a25 d0 to d15 busclk dramc dmac romc pwm0 pwm1 pwm1 dmarq0 to dmarq3 dmaak0 to dmaak3 tc0 to tc3
data sheet u15846ej1v0ds 8 pd70f3107a, 70f3107a(a) contents 1. changes from pd70f3107 data sheet (u14618e) ................................................................ 9 2. differences between products ............................................................................................. 9 3. pin functions................................................................................................................ ................. 10 3.1 port pins................................................................................................................... ................................. 10 3.2 non-port pins ............................................................................................................... ............................ 12 3.3 pin i/o circuits and recommended connection of unused pins........................................................ 15 4. electrical specifications.................................................................................................... ... 18 4.1 normal operation mode ....................................................................................................... ...................... 18 4.2 flash memory programming mode .................................................................................................. ......... 72 5. package drawing .............................................................................................................. .......... 75 6. recommended soldering conditions.................................................................................. 77 appendix notes on target system design.............................................................................. 78
data sheet u15846ej1v0ds 9 pd70f3107a, 70f3107a(a) 1. changes from pd70f3107 data sheet (u14618e) page description throughout addition of 161-pin plastic fbga (13 13) package p. 4 addition of 161-pin plastic fbga (13 13) pin configuration diagram p. 18 addition of storage temperature (t stg ) specification for fbga package p. 20 deletion of tdk recommended oscillator constant p. 24 addition of pll mode specifications (other than x10) to x1 input cycle (<1> t cyx ) pp.28, 30, 32, 34, 36 addition of description on ube, lbe signals in timing chart p. 29 relaxing of data input setup time (to address) (<39> t said ) and data input setup time (to rd) (<40> t srdid ) specifications p. 31 change of data output setup time (to uwr, lwr, iowr ) (<56> t sodwr ) specifications pp.37 to 41 addition of (5) sram, external rom, and external i/o access timing (vis--vis busclk signal) (when bcp bit of bcp register = 1 ) p. 68 addition of sin setup time (to sckn ) (<167> t ssisk ), sin hold time (from sckn ) (<168> t hsksi ), son output delay time (from sckn ) (<169> t dskso ), and son output hold time (from sckn ) (<170> t hskso ) specifications pp.69, 70 addition of (d) timing when ckpn, dapn bits of csicn register = 01 , (e) timing when ckpn, dapn bits of csicn register = 10 , and (f) timing when ckpn, dapn bits of csicn register = 11 p. 71 change of specification unit for overall error, zero-scale error, and full-scale error addition of integral linearity error and differential linearity error specifications p. 76 addition of 161-pin plastic fbga (13 13) package drawing p. 77 addition of 6. recommended soldering conditions p. 78 addition of appendix notes on target system design 2. differences between products rom product type size ram size flash memory programming pin package quality grade pd703103a none pd703105a 4 kb 144-pin lqfp pd703106a 128 kb pd703107a 256 kb 144-pin lqfp 161-pin fbga standard pd703106a(a) 128 kb pd703107a(a) mask rom 256 kb none 144-pin lqfp special pd70f3107a 144-pin lqfp 161-pin fbga standard pd70f3107a(a) flash memory 256 kb 10 kb provided (v pp ) 144-pin lqfp special cautions 1. there are differences in noise immunity and noise radiation between the flash memory version and mask rom version. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluation for commercial samples (not engineering samples) of the mask rom version. 2. when switching from the flash memory version to the mask rom version, write the same code to the free area of the internal rom.
data sheet u15846ej1v0ds 10 pd70f3107a, 70f3107a(a) 3. pin functions 3.1 port pins (1/2) pin name i/o function alternate function p00 pwm0 p01 ti000/intp000 p02 intp001 p03 to00 p04 dmarq0/intp100 p05 dmarq1/intp101 p06 dmarq2/intp102 p07 i/o port 0 8-bit i/o port input/output can be specified in 1-bit units. dmarq3/intp103 p10 pwm1 p11 intp010/ti010 p12 intp011 p13 i/o port 1 4-bit i/o port input/output can be specified in 1-bit units. to01 p20 input nmi p21 intp020/ti020 p22 intp021 p23 to02 p24 tc0/intp110 p25 tc1/intp111 p26 tc2/intp112 p27 i/o port 2 p20 is an input-only port. if a valid edge is input, it operates as an nmi input. also, the status of the nmi input is shown by bit 0 of the p2 register. p21 to p27 is a 7-bit i/o port. input/output can be specified in 1-bit units. tc3/intp113 p30 so2/intp130 p31 si2/intp131 p32 sck2/intp132 p33 txd2/intp133 p34 rxd2/intp120 p35 intp121 p36 intp122 p37 i/o port 3 8-bit i/o port input/output can be specified in 1-bit units. adtrg/intp123 p40 txd0/so0 p41 rxd0/si0 p42 sck0 p43 txd1/so1 p44 rxd1/si1 p45 i/o port 4 6-bit i/o port input/output can be specified in 1-bit units. sck1 p50 intp030/ti030 p51 intp031 p52 i/o port 5 3-bit i/o port input/output can be specified in 1-bit units. to03
data sheet u15846ej1v0ds 11 pd70f3107a, 70f3107a(a) (2/2) pin name i/o function alternate function p70 to p77 input port 7 8-bit input-only port ani0 to ani7 pbd0 to pbd3 i/o port bd 4-bit i/o port input/output can be specified in 1-bit units. dmaak0 to dmaak3 pcm0 wait pcm1 clkout/busclk pcm2 hldak pcm3 hldrq pcm4 refrq pcm5 i/o port cm 6-bit i/o port input/output can be specified in 1-bit units. selfref pct0 lcas/lwr/ldqm pct1 ucas/uwr/udqm pct4 rd pct5 we pct6 oe pct7 i/o port ct 6-bit i/o port input/output can be specified in 1-bit units. bcyst pcs0 cs0 pcs1 cs1/ras1 pcs2 cs2/iowr pcs3 cs3/ras3 pcs4 cs4/ras4 pcs5 cs5/iord pcs6 cs6/ras6 pcs7 i/o port cs 8-bit i/o port input/output can be specified in 1-bit units. cs7 pcd0 sdcke pcd1 sdclk pcd2 lbe/sdcas pcd3 i/o port cd 4-bit i/o port input/output can be specified in 1-bit units. ube/sdras pah0 to pah9 i/o port ah 8-/10-bit i/o port input/output can be specified in 1-bit units. a16 to a25 pal0 to pal15 i/o port al 8-/16-bit i/o port input/output can be specified in 1-bit units. a0 to a15 pdl0 to pdl15 i/o port dl 8-/16-bit i/o port input/output can be specified in 1-bit units. d0 to d15
data sheet u15846ej1v0ds 12 pd70f3107a, 70f3107a(a) 3.2 non-port pins (1/3) pin name i/o function alternate function to00 p03 to01 p13 to02 p23 to03 output pulse signal output of timer c0 to c3 p52 ti000 p01/intp000 ti010 p11/intp010 ti020 p21/intp020 ti030 input external count clock input of timer c0 to c3 p50/intp030 intp000 p01/ti000 intp001 input external maskable interrupt request input, or timer c0 external capture trigger input p02 intp010 p11/ti010 intp011 input external maskable interrupt request input, or timer c1 external capture trigger input p12 intp020 p21/ti020 intp021 input external maskable interrupt request input, or timer c2 external capture trigger input p22 intp030 p50/ti030 intp031 input external maskable interrupt request input, or timer c3 external capture trigger input p51 intp100 p04/dmarq0 intp101 p05/dmarq1 intp102 p06/dmarq2 intp103 p07/dmarq3 intp110 p24/tc0 intp111 p25/tc1 intp112 p26/tc2 intp113 p27/tc3 intp120 p34/rxd2 intp121 p35 intp122 p36 intp123 p37/adtrg intp130 p30/so2 intp131 p31/si2 intp132 p32/sck2 intp133 input external maskable interrupt request input p33/txd2 so0 p40/txd0 so1 p43/txd1 so2 output csi0 to csi2 serial transmission data output (3-wire) p30/intp130 si0 p41/rxd0 si1 p44/rxd1 si2 input csi0 to csi2 serial reception data input (3-wire) p31/intp131
data sheet u15846ej1v0ds 13 pd70f3107a, 70f3107a(a) (2/3) pin name i/o function alternate function sck0 p42 sck1 p45 sck2 i/o csi0 to csi2 serial clock i/o (3-wire) p32/intp132 txd0 p40/so0 txd1 p43/so1 txd2 output uart0 to uart2 serial transmission data output p33/intp133 rxd0 p41/si0 rxd1 p44/si1 rxd2 input uart0 to uart2 serial reception data input p34/intp120 pwm0 p00 pwm1 output pwm pulse signal output p10 ani0 to ani7 input analog inputs to the a/d converter p70 to p77 adtrg input a/d converter external trigger input p37/intp123 dmarq0 p04/intp100 dmarq1 p05/intp101 dmarq2 p06/intp102 dmarq3 input dma request signal input p07/intp103 dmaak0 pbd0 dmaak1 pbd1 dmaak2 pbd2 dmaak3 output dma acknowledge signal output pbd3 tc0 p24/intp110 tc1 p25/intp111 tc2 p26/intp112 tc3 output dma transfer termination (terminal count) signal output p27/intp113 nmi input non-maskable interrupt request signal input p20 mode0 ? mode1 ? mode2 input v850e/ma1 operating mode specification v pp v pp input flash memory programming power-supply application pin mode2 wait input control signal input that inserts a wait in the bus cycle pcm0 hldak output bus hold acknowledge output pcm2 hldrq input bus hold request input pcm3 refrq output refresh request signal output for dram pcm4 selfref input self refresh request input for dram pcm5 lcas output column address strobe signal output for dram lower data pct0/lwr/ldqm ucas output column address strobe signal output for dram higher data pct1/uwr/udqm lwr output external data lower byte write strobe signal output pct0/lcas/ldqm uwr output external data higher byte write strobe signal output pct1/ucas/udqm
data sheet u15846ej1v0ds 14 pd70f3107a, 70f3107a(a) (3/3) pin name i/o function alternate function ldqm output output disable/write mask signal output for sdram lower data pct0/lcas/lwr udqm output output disable/write mask signal output for sdram higher data pct1/ucas/uwr rd output external data bus read strobe signal output pct4 we output write enable signal output for dram pct5 oe output output enable signal output for dram pct6 bcyst output strobe signal output that shows the start of the bus cycle pct7 cs0 pcs0 cs1 pcs1/ras1 cs2 pcs2/iowr cs3 pcs3/ras3 cs4 pcs4/ras4 cs5 pcs5/iord cs6 pcs6/ras6 cs7 output chip select signal output pcs7 ras1 pcs1/cs1 ras3 pcs3/cs3 ras4 pcs4/cs4 ras6 output row address strobe signal output for dram pcs6/cs6 iowr output dma write strobe signal output pcs2/cs2 iord output dma read strobe signal output pcs5/cs5 sdcke output sdram clock enable signal output pcd0 sdclk output sdram clock signal output pcd1 sdcas output column address strobe signal output for sdram pcd2/lbe sdras output row address strobe signal output for sdram pcd3/ube lbe output external data bus lower byte enable signal output pcd2/sdcas ube output external data bus higher byte enable signal output pcd3/sdras d0 to d15 i/o 16-bit data bus for external memory pdl0 to pdl15 a0 to a15 pal0 to pal15 a16 to a25 output 26-bit address bus for external memory pah0 to pah9 reset input system reset input ? x1 input ? x2 ? connects the crystal resonator for system clock oscillation. in the case of an external source supplying the clock, it is input to x1. ? clkout output system clock output pcm1/busclk busclk output bus clock output pcm1/clkout cksel input input which specifies the clock generator's operating mode ? av ref input reference voltage applied to a/d converter av dd av dd ? positive power supply for a/d converter av ref av ss ? ground potential for a/d converter ? cv dd ? positive power supply for the dedicated clock generator ? cv ss ? ground potential for the dedicated clock generator ? v dd ? positive power supply ? v ss ? ground potential ?
data sheet u15846ej1v0ds 15 pd70f3107a, 70f3107a(a) 3.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins are shown in table 3-1. the i/o circuit configuration of each type is schematically shown in figure 3-1. it is recommended that 1 to 10 k ? resistors be used when connecting to v dd or v ss via a resistor. table 3-1. types of pin i/o circuits and recommended connection of unused pins (1/2) pin name i/o circuit type recommended connection p00/pwm0 5 p01/intp000/ti000 p02/intp001 5-ac p03/to00 5 p04/dmarq0/intp100 to p07/dmarq3/intp103 5-ac p10/pwm1 5 p11/intp010/ti010 p12/intp011 5-ac p13/to01 5 input: independently connect to v dd or v ss via a resistor. output: leave open. p20/nmi 2 connect to v ss directly. p21/intp020/ti020 p22/intp021 5-ac p23/to02 5 p24/tc0/intp110 to p27/tc3/intp113 p30/so2/intp130 p31/si2/intp131 p32/sck2/intp132 p33/txd2/intp133 p34/rxd2/intp120 p35/intp121 p36/intp122 p37/adtrg/intp123 5-ac p40/txd0/so0 5 p41/rxd0/si0 p42/sck0 5-ac p43/txd1/so1 5 p44/rxd1/si1 p45/sck1 p50/intp030/ti030 p51/intp031 5-ac p52/to03 5 input: independently connect to v dd or v ss via a resistor. output: leave open. p70/ani0 to p77/ani7 9 connect to v ss directly. pbd0/dmaak0 to pbd3/dmaak3 5 input: independently connect to v dd or v ss via a resistor. output: leave open.
data sheet u15846ej1v0ds 16 pd70f3107a, 70f3107a(a) table 3-1. types of pin i/o circuits and recommended connection of unused pins (2/2) pin name i/o circuit type recommended connection pcm0/wait 5 input: independently connect to v dd via a resistor. pcm1/clkout/busclk pcm2/hldak 5 input: independently connect to v dd or v ss via a resistor. output: leave open. pcm3/hldrq 5 input: independently connect to v dd via a resistor. pcm4/refrq 5 input: independently connect to v dd or v ss via a resistor. output: leave open. pcm5/selfref 5 input: independently connect to v ss via a resistor. pct0/lcas/lwr/ldqm pct1/ucas/uwr/udqm pct4/rd pct5/we pct6/oe pct7/bcyst pcs0/cs0 pcs1/cs1/ras1 pcs2/cs2/iowr pcs3/cs3/ras3 pcs4/cs4/ras4 pcs5/cs5/iord pcs6/cs6/ras6 pcs7/cs7 pcd0/sdcke pcd1/sdclk pcd2/lbe/sdcas pcd3/ube/sdras pah0/a16 to pah9/a25 pal0/a0 to pal15/a15 pdl0/d0 to pdl15/d15 5 input: independently connect to v dd or v ss via a resistor. output: leave open. mode0, mode1 mode2/v pp reset 2 cksel 1 ? av ss ? connect to v ss . av dd /av ref ? connect to v dd .
data sheet u15846ej1v0ds 17 pd70f3107a, 70f3107a(a) figure 3-1. pin i/o circuits type 1 type 2 type 5 p-ch n-ch in v dd in schmitt-triggered input with hysteresis characteristics p-ch n-ch v dd in/out data output disable input enable type 5-ac p-ch n-ch v dd in/out data output disable input enable in comparator + v ref (threshold voltage) p-ch n-ch input enable type 9
data sheet u15846ej1v0ds 18 pd70f3107a, 70f3107a(a) 4. electrical specifications 4.1 normal operation mode absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd v dd pin ? 0.5 to +4.6 v cv dd cv dd pin ? 0.5 to +4.6 v cv ss cv ss pin ? 0.5 to +0.5 v av dd av dd pin ? 0.5 to +4.6 v power supply voltage av ss av ss pin ? 0.5 to +0.5 v x1 pin, except mode2/v pp pin ? 0.5 to +6.0 v input voltage v i mode2/v pp pin ? 0.5 to +8.5 v clock input voltage v k x1, v dd = 3.3 v 0.3 v ? 0.5 to v dd + 1.0 v i ol per pin 4.0 ma output current, low total of all pins 100 ma i oh per pin ? 4.0 ma output current, high total of all pins ? 100 ma output voltage v o v dd = 3.3 v 0.3 v ? 0.5 to v dd + 0.5 v analog input voltage v wasn ani0 to ani7, v dd = 3.3 v 0.3 v ? 0.3 to av dd + 0.3 v operating ambient temperature t a ? 40 to +85 c lqfp package ? 60 to +150 c storage temperature t stg fbga package ? 40 to +125 c cautions 1. avoid direct connections among the ic device output (or i/o) pins and between v dd or v cc and gnd. however, direct connections among open-drain and open-collector pins are possible, as are direct connections to external circuits that have timing designed to prevent output conflict with pins that become high-impedance. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions shown below for dc characteristics and ac characteristics are within the range for normal operation and quality assurance. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o f c = 1 mhz unmeasured pins returned to 0 v. 15 pf
data sheet u15846ej1v0ds 19 pd70f3107a, 70f3107a(a) operating conditions operation mode internal operation clock frequency (f xx ) operating ambient temperature (t a ) power supply voltage (v dd ) direct mode 4 to 25 mhz ? 40 to +85 cv dd = 3.3 v 0.3 v pll mode 4 to 50 mhz ? 40 to +85 cv dd = 3.3 v 0.3 v recommended oscillator caution for the resonator selection and oscillator constant of the pd70f3107a(a), customers are requested to apply to the resonator manufacturer for evaluation. (a) ceramic resonator (i) murata mfg. co., ltd. (t a = ?40 to +85 c) x1 x2 c1 c2 r d oscillation frequency recommended circuit constant oscillation voltage range oscillation stabilization time (max.) type product f x (mhz) c1 (pf) c2 (pf) r d (k ? ) min. (v) max. (v) t ost (ms) cstcc4.00mg0h6 4.0 on-chip on-chip 0 3.0 3.6 0.09 surface mount cstcc5.00mg0h6 5.0 on-chip on-chip 0 3.0 3.6 0.09 csa4.00mg 4.0 30 30 0 3.0 3.6 0.05 cst4.00mgw 4.0 on-chip on-chip 0 3.0 3.6 0.05 csts0400mg06 4.0 on-chip on-chip 0 3.0 3.6 0.11 csa5.00mg 5.0 30 30 0 3.0 3.6 0.05 cst5.00mgw 5.0 on-chip on-chip 0 3.0 3.6 0.05 lead csts0500mg06 5.0 on-chip on-chip 0 3.0 3.6 0.11 cautions 1. connect the oscillator as closely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. thoroughly evaluate the matching between the pd70f3107a and the resonator.
data sheet u15846ej1v0ds 20 pd70f3107a, 70f3107a(a) (ii) kyocera corporation (t a = ?20 to +80 c) x1 x2 c1 c2 r d oscillation frequency recommended circuit constant oscillation voltage range oscillation stabilization time (max.) type product f x (mhz) c1 (pf) c2 (pf) r d (k ? ) min. (v) max. (v) t ost (ms) pbrc4.00ar-a 4.0 33 33 0 3.0 3.6 0.11 pbrc4.00br-a 4.0 on-chip on-chip 0 3.0 3.6 0.11 pbrc5.00ar-a 5.0 33 33 0 3.0 3.6 0.08 surface mount pbrc5.00br-a 5.0 on-chip on-chip 0 3.0 3.6 0.08 kbr-4.0msb 4.0 33 33 0 3.0 3.6 0.11 kbr-4.0mkc 4.0 on-chip on-chip 0 3.0 3.6 0.11 kbr-5.0msb 5.0 33 33 0 3.0 3.6 0.08 lead kbr-5.0mkc 5.0 on-chip on-chip 0 3.0 3.6 0.08 cautions 1. connect the oscillator as closely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. thoroughly evaluate the matching between the pd70f3107a and the resonator. (b) external clock input (t a = ?40 to +85 c) x1 x2 open external clock
data sheet u15846ej1v0ds 21 pd70f3107a, 70f3107a(a) dc characteristics (t a = ?40 to +85 c, v dd = 3.3 v 0.3 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit except for note 1 2.0 5.5 v input voltage, high v ih note 1 0.75v dd 5.5 v except for note 1 ?0.5 0.8 v input voltage, low v il note 1 ?0.5 0.2v dd v direct mode 0.8v dd v dd + 0.3 v clock input voltage, high v xh x1 pin pll mode 0.8v dd v dd + 0.3 v direct mode ?0.5 0.15v dd v clock input voltage, low v xl x1 pin pll mode ?0.5 0.15v dd v v t + note 1 , rising edge 2.0 v schmitt- triggered input threshold voltage v t ? note 1 , falling edge 1.0 v schmitt- triggered input hysteresis width v t + ? v t ? note 1 0.3 v i oh = ?2.5 ma 0.8v dd v output voltage, high v oh i oh = ?100 av dd ? 0.4 v output voltage, low v ol i ol = 2.5 ma 0.45 v input leakage current, high i lih v i = v dd , except for note 2 10 a input leakage current, low i lil v i = 0 v, except for note 2 ? 10 a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ? 10 a analog pin input leakage current i lwasn note 2 10 a v pp supply voltage v pp0 during normal operation 0 0.2v dd v direct mode 3.2 f xx + 30 4.8 f xx + 45 ma during normal operation i dd1 pll mode 3.2 f xx + 30 4.8 f xx + 45 ma direct mode 1.6 f xx + 20 2.4 f xx + 30 ma in halt mode i dd2 pll mode 1.6 f xx + 20 2.4 f xx + 30 ma direct mode 10 30 ma in idle mode i dd3 pll mode 10 30 ma ?40 c t a +40 c1060 a power supply current in stop mode i dd4 40 c < t a 85 c 600 a notes 1. p01/ti000/intp000, p02/intp001, p04/dmarq0/intp100 to p07/dmarq3/intp103, p11/ti010/intp010, p12/intp011, p21/ti020/intp020, p22/intp021, p24/tc0/intp110 to p27/tc3/intp113, p30/so2/intp130, p31/si2/intp131, p32/sck2/intp132, p33/txd2/intp133, p34/rxd2/intp120, p35/intp121, p36/intp122, p37/adtrg/intp123, p41/rxd0/si0, p42/sck0, p44/rxd1/si1, p45/sck1, p50/ti030/intp030, p51/intp031 2. p70/ani0 to p77/ani7 remarks 1. typ. values are reference values for when t a = 25 c and v dd = 3.3 v. the current does not include the current flowing through pull-up resistors. 2. f xx : cpu operation frequency
data sheet u15846ej1v0ds 22 pd70f3107a, 70f3107a(a) data retention characteristics (t a = ?40 to + + + + 85 c) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode and v dd = v dddr 1.5 3.6 v ?40 c t a +40 c1060 a data retention current i dddr v dd = v dddr 40 c < t a 85 c 600 a power supply voltage rise time t rvd 200 s power supply voltage fall time t fvd 200 s power supply voltage hold time (from stop mode setting) t hvd 0ms stop release signal input time t drel 0ns data retention high-level input voltage v ihdr note 0.8v dddr v dddr v data retention low-level input voltage v ildr note ?0.5 0.2v dddr v note p01/ti000/intp000, p02/intp001, p04/dmarq0/intp100 to p07/dmarq3/intp103, p11/ti010/intp010, p12/intp011, p21/ti020/intp020, p22/intp021, p24/tc0/intp110 to p27/tc3/intp113, p30/so2/intp130, p31/si2/intp131, p32/sck2/intp132, p33/txd2/intp133, p34/rxd2/intp120, p35/intp121, p36/intp122, p37/adtrg/intp123, p41/rxd0/si0, p42/sck0, p44/rxd1/si1, p45/sck1, p50/ti030/intp030, p51/intp031 remark typ. values are reference values for when t a = 25 c. t hvd v dddr t drel v ihdr v ihdr v ildr t fvd t rvd v dd nmi (input) nmi (input) stop mode setup reset (input) (released at falling edge) (released at rising edge)
data sheet u15846ej1v0ds 23 pd70f3107a, 70f3107a(a) ac characteristics (t a = ?40 to + + + + 85 c, v dd = 3.3 v 0.3 v, v ss = 0 v, output pin load capacitance: c l = 50 pf) ac test input points (a) p01/ti000/intp000, p02/intp001, p04/dmarq0/intp100 to p07/dmarq3/intp103, p11/ti010/intp010, p12/intp011, p21/ti020/intp020, p22/intp021, p24/tc0/intp110 to p27/tc3/intp113, p30/so2/intp130, p31/si2/intp131, p32/sck2/intp132, p33/txd2/intp133, p34/rxd2/intp120, p35/intp121, p36/intp122, p37/adtrg/intp123, p41/rxd0/si0, p42/sck0, p44/rxd1/si1, p45/sck1, p50/ti030/intp030, p51/intp031 (b) other than (a) above ac test output test points load condition caution in cases where the load capacitance is greater than 50 pf due to the circuit configuration, insert a buffer or other element to reduce the device?s load capacitance to 50 pf or lower. c l = 50 pf dut (device under test) v dd 0.75v input signal dd 0.2v dd 0.75v dd 0.2v dd 0 v test points 2.0 v 0.8 v 2.0 v 0.8 v v dd input signal 0 v test points 0.7v dd 0.2v dd 0.7v dd 0.2v dd v dd output signal 0 v test points
data sheet u15846ej1v0ds 24 pd70f3107a, 70f3107a(a) (1) clock timing (1/2) parameter symbol conditions min. max. unit direct mode 20 125 ns 10 200 250 ns x1 input cycle <1> t cyx pll mode other than 10 150 250 ns direct mode 5 ns x1 input high-level width <2> t wxh pll mode 50 ns direct mode 5 ns x1 input low-level width <3> t wxl pll mode 50 ns direct mode 4 ns x1 input rise time <4> t xr pll mode 10 ns direct mode 4 ns x1 input fall time <5> t xf pll mode 10 ns clkout output cycle <6> t cyk1 20 250 ns clkout high-level width <7> t wkh1 0.5t ? 5ns clkout low-level width <8> t wkl1 0.5t ? 6ns clkout rise time <9> t kr1 5ns clkout fall time <10> t kf1 4ns delay time from x1 to clkout <11> t dkx 40 ns delay time from x1 to sdclk <12> t dsx 40 ns sdclk output cycle <13> t cyk2 20 250 ns sdclk high-level width <14> t wkh2 0.5t ? 5ns sdclk low-level width <15> t wkl2 0.5t ? 6ns sdclk rise time <16> t kr2 5ns sdclk fall time <17> t kf2 4ns busclk rise time <18> t kr3 5ns busclk fall time <19> t kf3 4ns remarks 1. t = t cyk 2. the phase difference between clkout and sdclk, and between clkout and busclk cannot be defined.
data sheet u15846ej1v0ds 25 pd70f3107a, 70f3107a(a) (1) clock timing (2/2) remark the cycle of busclk varies depending on the bus cycle. (2) output waveform (other than x1 and clkout) parameter symbol conditions min. max. unit output rise time <20> t or 5ns output fall time <21> t of 4ns <21> <20> signals other than x1 and clkout x1 <2> <1> <3> <5> <4> x1 (direct mode) (pll mode) <5> <1> <2> <3> <4> <11> <11> <12> clkout (output) <8> <9> <7> <10> <6> sdclk (output) <15> <16> <14> <17> <13> busclk (output) <18> <19>
data sheet u15846ej1v0ds 26 pd70f3107a, 70f3107a(a) (3) reset timing parameter symbol conditions min. max. unit reset pin high-level width <22> t wrsh 500 ns at power-on and at stop mode release 500 + t os ns reset pin low-level width <23> t wrsl other than at power-on and at stop mode release 500 ns remark t os : oscillation stabilization time caution thoroughly evaluate the oscillation stabilization time. <22> <23> reset (input)
data sheet u15846ej1v0ds 27 pd70f3107a, 70f3107a(a) (4) sram, external rom, and external i/o access timing (when bcp bit of bcp register = 0) (a) access timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit address, csn output delay time (from clkout ) 2 13 ns address, csn output delay time (from sdclk ) <24> t dka 013ns address, csn output hold time (from clkout ) 2 13 ns address, csn output hold time (from sdclk ) <25> t hka 013ns rd, iord delay time (from clkout ) 2 13 ns rd, iord delay time (from sdclk ) <26> t dkrdl 013ns rd, iord delay time (from clkout ) 2 13 ns rd, iord delay time (from sdclk ) <27> t hkrdh 013ns uwr, lwr, iowr delay time (from clkout ) 2 13 ns uwr, lwr, iowr delay time (from sdclk ) <28> t dkwrl 013ns uwr, lwr, iowr delay time (from clkout ) 2 13 ns uwr, lwr, iowr delay time (from sdclk ) <29> t hkwrh 013ns bcyst delay time (from clkout ) 2 13 ns bcyst delay time (from sdclk ) <30> t dkbsl 013ns bcyst delay time (from clkout ) 2 13 ns bcyst delay time (from sdclk ) <31> t hkbsh 013ns wait setup time (to clkout )8ns wait setup time (to sdclk ) <32> t swk 10 ns wait hold time (from clkout )2ns wait hold time (from sdclk ) <33> t hkw 2ns data input setup time (to clkout )8ns data input setup time (to sdclk ) <34> t skid 10 ns data input hold time (from clkout )2ns data input hold time (from sdclk ) <35> t hkid 2ns data output delay time (from clkout ) 2 13 ns data output delay time (from sdclk ) <36> t dkod1 013ns data output delay time (from clkout ) 2 13 ns data output delay time (from sdclk ) <37> t dkod2 013ns data float delay time (from clkout ) 2 13 ns data float delay time (from sdclk ) <38> t hkod 013ns remarks 1. maintain at least one of the data input hold times, t hrdid or t hkid . 2. n = 0 to 7
data sheet u15846ej1v0ds 28 pd70f3107a, 70f3107a(a) (a) access timing (sram, external rom, external i/o) (2/2) remarks 1. this is the timing when the number of waits based on the dwc0 and dwc1 registers is zero. 2. broken lines indicate high impedance. 3. n = 0 to 7 clkout (output) [ read ] [ write ] [ write ] [ read ] rd, iord (output) t1 tw t2 <24> <25> <30> <26> <28> <29> <27> <35> <34> <37> <38> <32> <33> <32> <33> a0 to a25 (output) uwr, lwr, iowr (output) d0 to d15 (i/o) d0 to d15 (i/o) <31> <29> <38> <27> <30> <26> <28> <36> <36> sdclk (output) csn (output) wait (input) bcyst (output) ube, lbe (output)
data sheet u15846ej1v0ds 29 pd70f3107a, 70f3107a(a) (b) read timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit data input setup time (from address) <39> t said (2 + w + w d + w as )t ? 19 ns data input setup time (from rd) <40> t srdid (1.5 + w + w d )t ? 19 ns rd, iord low-level width <41> t wrdl (1.5 + w + w d )t ? 10 ns rd, iord high-level width <42> t wrdh (0.5 + w as + i)t ? 10 ns delay time from address, csn, to rd, iord <43> t dard (0.5 + w as )t ? 10 ns delay time from rd, iord to address <44> t drda it ns data input hold time (from rd, iord ) <45> t hrdid 0ns delay time from rd, iord to data output <46> t drdod (0.5 + i)t ? 10 ns wait setup time (from address) <47> t saw note (1 + w as )t ? 21 ns wait setup time (from bcyst ) <48> t sbsw note (1 + w as )t ? 21 ns wait hold time (from bcyst ) <49> t hbsw note t ? 10 ns wait high-level width <50> t wwh t ? 10 ns data output hold time (from uwr, lwr, iowr ) <57> t hwrod (0.5 + i)t ? 8ns note for the first wait sampling when the wait count based on the dwc0 and dwc1 registers is zero. remarks 1. t = t cyk 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. maintain at least one of the data input hold times t hrdid or t hkid 5. n = 0 to 7 6. i: idle state count 7. w as : address setup wait count based on the asc register
data sheet u15846ej1v0ds 30 pd70f3107a, 70f3107a(a) (b) read timing (sram, external rom, external i/o) (2/2) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait count based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7 clkout (output) csn (output) a0 to a25 (output) uwr, lwr, iowr rd, iord (output) d0 to d15 (i/o) t1 tw t2 <45> <42> <41> <44> <46> <39> <40> <43> <47> <48> ti tasw <49> <57> <50> wait (input) bcyst (output) (output) ube, lbe (output)
data sheet u15846ej1v0ds 31 pd70f3107a, 70f3107a(a) (c) write timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit wait setup time (from address) <47> t saw note (1 + w as )t ? 21 ns wait setup time (from bcyst ) <48> t sbsw note (1 + w as )t ? 21 ns wait hold time (from bcyst ) <49> t hbsw note t ? 10 ns wait high-level width <50> t wwh t ? 10 ns delay time from address, csn to uwr, lwr, iowr <51> t dawr (0.5 + w as )t ? 10 ns address setup time (to uwr, lwr, iowr ) <52> t sawr (1.5 + w + w d + w as )t ? 10 ns delay time from uwr, lwr, iowr to address <53> t dwra (0.5 + i)t ? 10 ns uwr, lwr, iowr high-level width <54> t wwrh (0.5 + i + w as )t ? 10 ns uwr, lwr, iowr low-level width <55> t wwrl (1 + w + w d )t ? 10 ns data output setup time (to uwr, lwr, iowr ) <56> t sodwr (0.5 + w + w d )t ? 10 ns data output hold time (from uwr, lwr, iowr ) <57> t hwrod (0.5 + i)t ? 8ns note for the first wait sampling when the wait count based on the dwc0 and dwc1 registers is zero. remarks 1. t = t cyk 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. n = 0 to 7 5. i: idle state count 6. w as : address setup wait count based on the asc register
data sheet u15846ej1v0ds 32 pd70f3107a, 70f3107a(a) (c) write timing (sram, external rom, external i/o) (2/2) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait count based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7 <54> <52> <53> write write <51> <55> <56> csn (output) a0 to a25 (output) uwr, lwr, iowr rd, iord (output) <57> clkout (output) t1 tw t2 ti tasw <47> <48> wait (input) bcyst (output) <49> <50> (output) d0 to d15 (i/o) read write d0 to d15 (i/o) ube, lbe (output)
data sheet u15846ej1v0ds 33 pd70f3107a, 70f3107a(a) (d) dma flyby transfer timing (sram external i/o transfer) (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8ns wait hold time (from clkout ) <33> t hkw 0ns rd low-level width <41> t wrdl (1.5 + w + w d )t ? 10 ns rd high-level width <42> t wrdh (0.5 + w as + i)t ? 10 ns delay time from address, csn to rd <43> t dard (0.5 + w as )t ? 10 ns delay time from rd to address <44> t drda it ns delay time from rd to data output <46> t drdod (0.5 + i)t ? 10 ns wait setup time (from address) <47> t saw note (1 + w as )t ? 21 ns wait setup time (from bcyst ) <48> t sbsw note (1 + w as )t ? 21 ns wait hold time (from bcyst ) <49> t hbsw note t ? 10 ns wait high-level width <50> t wwh t ? 10 ns delay time from address to iowr <51> t dawr (0.5 + w as )t ? 10 ns address setup time (to iowr ) <52> t sawr (1.5 + w + w d + w as )t ? 10 ns delay time from iowr to address <53> t dwra (1.5 + i)t ? 10 ns iowr high-level width <54> t wwrh (0.5 + i + w as )t ? 10 ns iowr low-level width <55> t wwrl (1 + w + w d )t ? 10 ns delay time from iowr to rd <58> t diwrrd 1.5t ? 10 ns delay time from dmaakm to iowr <59> t ddawr (0.5 + w as )t ? 10 ns delay time from iowr to dmaakm <60> t dwrda (1.5 + i)t ? 10 ns note for the first wait sampling when the number of waits based on the dwc0 and dwc1 registers is zero. remarks 1. t = t cyk 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. n = 0 to 7, m = 0 to 3 5. i: idle state count 6. w as : address setup wait count based on the asc register
data sheet u15846ej1v0ds 34 pd70f3107a, 70f3107a(a) (d) dma flyby transfer timing (sram external i/o transfer) (2/2) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait count based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 <42> <41> <54> <51> <52> <43> <59> <55> <32> <33> <32> <33> <47> dmaakm (output) iord (output) iowr (output) rd (output) uwr, lwr (output) wait (input) bcyst (output) <48> csn (output) a0 to a25 (output) <49> clkout (output) t1 tw t2 tasw <44> <60> <53> <46> ti tf <58> <50> d0 to d15 (i/o) ube, lbe (output)
data sheet u15846ej1v0ds 35 pd70f3107a, 70f3107a(a) (e) dma flyby transfer timing (external i/o sram transfer) (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8ns wait hold time (from clkout ) <33> t hkw 0ns iord low-level width <41> t wrdl (2 + w + w d )t ? 10 ns iord high-level width <42> t wrdh (1 + i + w as )t ? 10 ns delay time from address, csn to iord <43> t dard (0.5 + w as )t ? 10 ns delay time from iord to address <44> t drda (0.5 + i) t ? 10 ns delay time from iord to data output <46> t drdod (1 + i)t ? 10 ns wait setup time (from address) <47> t saw note (1 + w as )t ? 21 ns wait setup time (from bcyst ) <48> t sbsw note (1 + w as )t ? 21 ns wait hold time (from bcyst ) <49> t hbsw note t ? 10 ns wait high-level width <50> t wwh t ? 10 ns delay time from address to uwr, lwr <51> t dawr (0.5 + w as )t ? 10 ns address setup time (to uwr, lwr ) <52> t sawr (1.5 + w + w d + w as )t ? 10 ns delay time from uwr, lwr to address <53> t dwra (0.5 + i)t ? 10 ns uwr, lwr high-level width <54> t wwrh (0.5 + i + w as )t ? 10 ns uwr, lwr low-level width <55> t wwrl (1 + w + w d )t ? 10 ns delay time from uwr, lwr to iord <61> t dwrird t ? 10 ns delay time from dmaakm to iord <62> t ddard (0.5 + w as )t ? 10 ns delay time from iord to dmaakm <63> t drdda (0.5 + i)t ? 10 ns note for first wait sampling when wait count based on the dwc0 and dwc1 registers is zero. remarks 1. t = t cyk 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. n = 0 to 7, m = 0 to 3 5. i: count of idle states inserted when a write cycle follows a read cycle 6. w as : address setup wait count based on the asc register
data sheet u15846ej1v0ds 36 pd70f3107a, 70f3107a(a) (e) dma flyby transfer timing (external i/o sram transfer) (2/2) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait count based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 <54> <55> <53> <42> <63> <44> <41> <46> d0 to d15 (i/o) <51> <52> <62> <43> rd (output) dmaakm (output) iowr (output) iord (output) csn (output) a0 to a25 (output) uwr, lwr (output) <32> <33> <32> <33> <47> wait (input) bcyst (output) <48> <49> clkout (output) t1 tw t2 ti tasw tf <61> <50> ube, lbe (output)
data sheet u15846ej1v0ds 37 pd70f3107a, 70f3107a(a) (5) sram, external rom, and external i/o access timing (vis--vis busclk signal) (when bcp bit of bcp register = 1) (a) access timing (sram, external rom, external i/o) parameter symbol conditions min. max. unit wait setup time (to busclk ) <32> t swk 8ns wait hold time (from busclk ) <33> t hkw 0.5t ? 4ns wait hold time (from busclk ) <172> t hkw1 t + 2 ns data input setup time (to busclk ) <34> t skid 8ns data input hold time (from busclk ) <35> t hkid 0.5t ? 4ns data output delay time (from busclk ) <36> t dkod1 t ? 5t + 8 ns data output delay time (from busclk ) <37> t dkod2 ? 5+8ns data float delay time (from busclk ) <38> t hkod 0.5t ? 4 0.5t + 8 ns remarks 1. maintain at least one of the data input hold times, t hrdid or t hkid . 2. t = internal system clock cycle (this does not mean x2 bus cycle). remarks 1. this is the timing when the number of waits based on the dwc0 and dwc1 registers is zero. 2. broken lines indicate high impedance. internal system clock t1 tw t2 t1 tw t2 wait (input) <32> <33> <32> <172> <37> busclk (output) <38> <34> <35> <36> <37> [ when read ] d0 to d15 (i/o) [when written] d0 to d15 (i/o)
data sheet u15846ej1v0ds 38 pd70f3107a, 70f3107a(a) (b) read timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit data input setup time (to address) <39> t said (2 + w + w d + w as )t ? 19 ns data input setup time (to rd) <40> t srdid (1.5 + w + w d )t ? 19 ns rd, iord low-level width <41> t wrdl (1.25 + w + w d )t ? 10 ns rd, iord high-level width <42> t wrdh (0.75 + w as + i)t ? 10 ns delay time from address, csn, to rd, iord <43> t dard (0.75 + w as )t ? 10 ns delay time from rd, iord to address <44> t drda it ns data input hold time (from rd, iord ) <45> t hrdid 0ns delay time from rd, iord to data output <46> t drdod (0.25 + i)t ? 10 ns wait setup time (to address) <47> t saw note (1 + w as )t ? 21 ns wait setup time (to bcyst ) <48> t sbsw note (1 + w as )t ? 21 ns wait hold time (from bcyst ) <49> t hbsw note 0.5t ? 10 ns wait high-level width <50> t wwh t ? 10 ns data output hold time (from uwr, lwr, iowr ) <57> t hwrod (0.25 + i)t ? 8ns note for the first wait sampling when the wait count based on the dwc0 and dwc1 registers is zero. remarks 1. t = busclk cycle (internal system clock/2) 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. maintain at least one of the data input hold times t hrdid or t hkid 5. n = 0 to 7 6. i: idle state count 7. w as : address setup wait count based on the asc register
data sheet u15846ej1v0ds 39 pd70f3107a, 70f3107a(a) (b) read timing (sram, external rom, external i/o) (2/2) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait count based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7 clkout (output) csn (output) a0 to a25 (output) uwr, lwr, iowr rd, iord (output) d0 to d15 (i/o) t1 tw t2 <45> <42> <41> <44> <46> <39> <40> <43> <47> <48> ti tasw <49> <57> <50> wait (input) bcyst (output) (output) ube, lbe (output)
data sheet u15846ej1v0ds 40 pd70f3107a, 70f3107a(a) (c) write timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit wait setup time (to address) <47> t saw note (1 + w as )t ? 21 ns wait setup time (to bcyst ) <48> t sbsw note (1 + w as )t ? 21 ns wait hold time (from bcyst ) <49> t hbsw note 0.5t ? 10 ns wait high-level width <50> t wwh t ? 10 ns delay time from address, csn to uwr, lwr, iowr <51> t dawr (0.75 + w as )t ? 10 ns address setup time (to uwr, lwr, iowr ) <52> t sawr (1.75 + w + w d + w as )t ? 10 ns delay time from uwr, lwr, iowr to address <53> t dwra (0.25 + i)t ? 10 ns uwr, lwr, iowr high-level width <54> t wwrh (1 + i + w as )t ? 10 ns uwr, lwr, iowr low-level width <55> t wwrl (1 + w + w d )t ? 10 ns data output setup time (to uwr, lwr, iowr ) <56> t sodwr (1.25 + w + w d )t ? 10 ns data output hold time (from uwr, lwr, iowr ) <57> t hwrod (0.25 + i)t ? 8ns note for the first wait sampling when the wait count based on the dwc0 and dwc1 registers is zero. remarks 1. t = busclk cycle (internal system clock/2) 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. n = 0 to 7 5. i: idle state count 6. w as : address setup wait count based on the asc register
data sheet u15846ej1v0ds 41 pd70f3107a, 70f3107a(a) (c) write timing (sram, external rom, external i/o) (2/2) remarks 1. this is the timing when the wait count based on the dwc0 and dwc1 registers is zero, the idle state count based on the bcc register is 1, and the wait count based on the asc register is 1. 2. broken lines indicate high impedance. 3. n = 0 to 7 <54> <52> <53> write write <51> <55> <56> csn (output) a0 to a25 (output) uwr, lwr, iowr rd, iord (output) <57> clkout (output) t1 tw t2 ti tasw <47> <48> wait (input) bcyst (output) <49> <50> (output) d0 to d15 (i/o) read write d0 to d15 (i/o) ube, lbe (output)
data sheet u15846ej1v0ds 42 pd70f3107a, 70f3107a(a) (6) page rom access timing (a) 8-bit bus width (half-word/word access) and 16-bit bus width (word access) (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8ns wait hold time (from clkout ) <33> t hkw 0ns data input setup time (to clkout ) <34> t skid 8ns data input hold time (from clkout ) <35> t hkid 0ns off-page data input setup time (to address) <39> t said (2 + w + w d + w as )t ? 21 ns off-page data input setup time (from rd) <40> t srdid (1.5 + w + w d )t ? 21 ns data input hold time (from rd ) <45> t hrdid 0ns delay time from rd to data output <46> t drdod (0.5 + i)t ? 10 ns on-page data input setup time (from address) <64> t soaid (2 + w + w pr + w as )t ? 21 ns remarks 1. t = t cyk 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. w pr : wait count based on the prc register 5. i: count of idle states inserted when a write cycle follows a read cycle 6. w as : address setup wait count based on the asc register 7. maintain at least one of the data input hold times t hkid or t hrdid
data sheet u15846ej1v0ds 43 pd70f3107a, 70f3107a(a) (a) 8-bit bus width (half-word/word access) and 16-bit bus width (word access) (2/2) note on-page and off-page addresses are as follows. prc register ma6 ma5 ma4 ma3 on-page address off-page address 0 0 0 0 a0 to a2 a3 to a25 0 0 0 1 a0 to a3 a4 to a25 0 0 1 1 a0 to a4 a5 to a25 0 1 1 1 a0 to a5 a6 to a25 1 1 1 1 a0 to a6 a7 to a25 remarks 1. this is the timing for the following case. wait count based on the dwc0 and dwc1 registers (tdw): 1 wait count based on the prc register (tprw): 1 wait count based on the asc register (tasw): 1 2. broken lines indicate high impedance. 3. n = 0 to 7 csn (output) clkout (output) t1 tdw tw t2 <39> <40> <35> <33> <32> <32> <33> d0 to d15 (i/o) uwr, lwr (output) rd (output) wait (input) bcyst (output) <34> to1 tprw tw to2 <64> <34> <35> <45> <33> <32> <33> <32> tasw tasw <46> address (output) note
data sheet u15846ej1v0ds 44 pd70f3107a, 70f3107a(a) (b) 8-bit bus width (byte access) and 16-bit bus width (byte/half-word access) (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8ns wait hold time (from clkout ) <33> t hkw 0ns data input setup time (to clkout ) <34> t skid 8ns data input hold time (from clkout ) <35> t hkid 0ns off-page data input setup time (to address) <39> t said (2 + w + w d + w as )t ? 21 ns off-page data input setup time (from rd) <40> t srdid (1.5 + w + w d )t ? 21 ns off-page rd low-level width <180> t wrdl (1.5 + w + w d )t ? 10 ns rd high-level width <181> t wrdh (0.5 + w as )t ? 10 ns data input hold time (from rd ) <45> t hrdid 0ns delay time from rd to data output <46> t drdod (0.5 + i)t ? 10 ns on-page rd low-level width < 182> t wordl (1.5 + w + w pr )t ? 10 ns on-page data input setup time (from address) <64> t soaid (2 + w + w pr + w as )t ? 21 ns on-page data input setup time (from rd) < 183> t sordid (1.5 + w + w pr )t ? 21 ns remarks 1. t = t cyk 2. w: wait count based on wait 3. w d : wait count based on the dwc0 and dwc1 registers 4. w pr : wait count based on the prc register 5. i: count of idle states inserted when a write cycle follows a read cycle 6. w as : address setup wait count based on the asc register 7. maintain at least one of the data input hold times t hkid or t hrdid
data sheet u15846ej1v0ds 45 pd70f3107a, 70f3107a(a) (b) 8-bit bus width (byte access) and 16-bit bus width (byte/half-word access) (2/2) csn (output) clkout (output) t1 tdw tw t2 <39> <40> <35> <33> <32> <32> <33> d0 to d15 (i/o) uwr, lwr (output) rd (output) wait (input) bcyst (output) <34> to1 tprw tw to2 <64> <34> <35> <45> <33> <32> <33> <32> tasw tasw <46> address (output) note <180> <181> <183> <182> note on-page and off-page addresses are as follows. prc register ma6 ma5 ma4 ma3 on-page address off-page address 0 0 0 0 a0 to a2 a3 to a25 0 0 0 1 a0 to a3 a4 to a25 0 0 1 1 a0 to a4 a5 to a25 0 1 1 1 a0 to a5 a6 to a25 1 1 1 1 a0 to a6 a7 to a25 remarks 1. this is the timing for the following case. wait count based on the dwc0 and dwc1 registers (tdw): 1 wait count based on the prc register (tprw): 1 wait count based on the asc register (tasw): 1 2. broken lines indicate high impedance. 3. n = 0 to 7
data sheet u15846ej1v0ds 46 pd70f3107a, 70f3107a(a) (7) dram access timing (a) read timing (edo dram) (1/3) parameter symbol conditions min. max. unit data input setup time (to clkout ) <34> t skid 8ns data input hold time (from clkout ) <35> t hkid 0ns delay time from oe to data output <46> t drdod (1 + i)t ? 10 ns read/write cycle time <65> t hpc (1 + w da + w cp )t ? 10 ns row address setup time <66> t asr 0.5t ? 10 ns row address hold time <67> t rah (0.5 + w rh )t ? 10 ns column address setup time <68> t asc 0.5t ? 10 ns column address hold time <69> t cah (0.5 + w da )t ? 10 ns w rp = 0 t ? 10 ns ras precharge time <70> t rp w rp 1w rp t ? 10 ns column address read time (to ras ) <71> t ral (1.5 + w cp + w da )t ? 10 ns cas hold time <72> t csh (1.5 + w rh + w da )t ? 10 ns delay time from ras to column address <73> t rad (0.5 + w rh )t ? 10 ns delay time from ras to cas <74> t rcd (1 + w rh )t ? 10 ns w rp = 0 1.5t ? 10 ns cas to ras precharge time <75> t crp w rp 1 (0.5 + w rp )t ? 10 ns ras hold time from cas precharge <76> t rhcp (1.5 + w cp + w da )t ? 10 ns w rp = 0 (3 + w rh )t ? 10 ns we setup time (to cas ) <77> t rcs w rp 1(2 + w rp + w rh )t ? 10 ns we hold time (from ras ) <78> t rrh (1 + i)t ? 10 ns we hold time (from cas ) <79> t rch (1.5 + i)t ? 10 ns ras pulse width off-page <80> t rasp (2 + w rh + w da )t ? 10 ns cas pulse width <81> t hcas (0.5 + w da )t ? 10 ns cas precharge time <82> t cp (0.5 + w cp )t ? 10 ns w rp = 0 (2.5 + w rh + w da )t ? 10 ns off-page <83> t och1 w rp 1 (1.5 + w rp + w rh + w da )t ? 10 ns cas hold time from oe on-page <84 >t och2 (0.5 + w cp + w da )t ? 10 ns access time to cas precharge <85> t acp (1.5 + w cp + w da )t ? 21 ns data input hold time (from cas ) <86> t dhc 0ns cas access time <87> t cac (1 + w da )t ? 21 ns access time from column address <88> t aa (1.5 + w da )t ? 21 ns
data sheet u15846ej1v0ds 47 pd70f3107a, 70f3107a(a) (a) read timing (edo dram) (2/3) parameter symbol conditions min. max. unit w rp = 0 (3 + w rp + w rh + w da )t ? 21 ns off-page <89> t oea1 w rp 1(2 + w rp + w rh + w da )t ? 21 ns output enable access time on-page <90> t oea2 (1 + w cp + w da )t ? 21 ns ras access time <91> t rac (2 + w rh + w da ) t ? 21 ns output buffer turn-off delay time (from oe) <92> t oez 0ns cautions 1. at least one clock is inserted in w rp by default regardless of the setting of the rpc1n and rpc0n bits in the scrn register (n = 1, 3, 4, or 6) 2. the wait signal cannot be controlled using the bcyst signal when using edo dram. remarks 1. t = t cyk 2. w da : wait count based on the dac1n and dac0n bits of the scrn register (n = 1, 3, 4, 6) 3. w cp : wait count based on the cpc1n and cpc0n bits of the scrn register (n = 1, 3, 4, 6) 4. w rp : wait count based on the rpc1n and rpc0n bits of the scrn register (n = 1, 3, 4, 6) 5. w rh : wait count based on the rhc1n and rhc0n bits of the scrn register (n = 1, 3, 4, 6) 6. i: idle state count
data sheet u15846ej1v0ds 48 pd70f3107a, 70f3107a(a) (a) read timing (edo dram) (3/3) clkout (output) <67> <66> <70> <80> <73> <71> <68> <69> <82> <75> <74> <72> <81> <76> a0 to a25 (output) d0 to d15 (i/o) trpw note 1 t1 trhw t2 tdaw tcpw tb tdaw te <88> <79> <81> <65> <77> <85> <87> <84> <83> <46> <34> <35> <34> <88> <91> <89> <90> <35> <92> rasn (output) lcas (output) ucas (output) we (output) oe (output) bcyst (output) wait (input) <78> <87> <86> data data row address column address column address note 2 notes 1. at least one clock is inserted in trpw. 2. during on-page access from other cycles while ras is low level. remarks 1. this is the timing for the following case. wait count based on the rpc1n and rpc0n bits of the scrn register (trpw): 1 wait count based on the rhc1n and rhc0n bits of the scrn register (trhw): 1 wait count based on the dac1n and dac0n bits of the scrn register (tdaw): 1 wait count based on the cpc1n and cpc0n bits of the scrn register (tcpw): 1 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6
data sheet u15846ej1v0ds 49 pd70f3107a, 70f3107a(a) (b) write timing (edo dram) (1/2) parameter symbol conditions min. max. unit w cp = 0 (2 + w da )t ? 10 ns read/write cycle time <65> t hpc w cp 1(1 + w da + w cp )t ? 10 ns row address setup time <66> t asr 0.5t ? 10 ns row address hold time <67> t rah (0.5 + w rh )t ? 10 ns column address setup time <68> t asc 0.5t ? 10 ns column address hold time <69> t cah (0.5 + w da )t ? 10 ns w rp = 0 t ? 10 ns ras precharge time <70> t rp w rp 1w rp t ? 10 ns w cp = 0 (2.5 + w da )t ? 10 ns column address read time (to ras ) <71> t ral w cp 1 (1.5 + w cp + w da )t ? 10 ns cas hold time <72> t csh (1.5 + w rh + w da )t ? 10 ns delay time from ras to column address <73> t rad (0.5 + w rh )t ? 10 ns delay time from ras to cas <74> t rcd (1 + w rh )t ? 10 ns w rp = 0 1.5t ? 10 ns cas to ras precharge time <75> t crp w rp 1 (0.5 + w rp )t ? 10 ns w cp = 0 (2.5 + w da )t ? 10 ns ras hold time from cas precharge <76> t rhcp w cp 1 (1.5 + w cp + w da )t ? 10 ns ras pulse width off-page <80> t rasp (2 + w rh + w da )t ? 10 ns cas pulse width <81> t hcas (0.5 + w da )t ? 10 ns w cp = 0 1.5t ? 10 ns cas precharge time <82> t cp w cp 1 (0.5 + w cp )t ? 10 ns ras hold time <93> t rsh (1 + w da )t ? 10 ns w rp = 0 (2 + w rh )t ? 10 ns off-page <94> t wcs1 w rp 1(1 + w rp + w rh )t ? 10 ns w cp = 0 t ? 10 ns we setup time (to cas ) on-page <95> t wcs2 w cp 1w cp t ? 10 ns we hold time (from cas ) <96> t wch (1 + w da )t ? 10 ns off-page <97> t ds1 (1.5 + w rh )t ? 10 ns w cp = 0 1.5t ? 10 ns data setup time (to cas ) on-page <98> t ds2 w cp 1 (0.5 + w cp )t ? 10 ns data hold time (from cas ) <99> t dh (0.5 + w da )t ? 10 ns w cp = 0 (2 + w da )t ? 10 ns we pulse width on-page <100> t wp w cp 1(1 + w da + w cp )t ? 10 ns w cp = 0 (2 + w da )t ? 10 ns we read time (to ras ) on-page <101> t rwl w cp 1(1 + w da + w cp )t ? 10 ns w cp = 0 (1.5 + w da )t ? 10 ns we read time (to cas ) on-page <102> t cwl w cp 1 (0.5 + w da + w cp )t ? 10 ns
data sheet u15846ej1v0ds 50 pd70f3107a, 70f3107a(a) cautions 1. at least one clock is inserted in w rp by default regardless of the setting of the rpc1n and rpc0n bits in the scrn register (n = 1, 3, 4, 6). 2. at least one clock is inserted in w cp by default regardless of the setting of the cpc1n and cpc0n bits in the scrn register (n = 1, 3, 4, 6). 3. the wait signal cannot be controlled using the bcyst signal when using edo dram. remarks 1. t = t cyk 2. w da : wait count based on the dac1n and dac0n bits of the scrn register (n = 1, 3, 4, 6) 3. w cp : wait count based on the cpc1n and cpc0n bits of the scrn register (n = 1, 3, 4, 6) 4. w rp : wait count based on the rpc1n and rpc0n bits of the scrn register (n = 1, 3, 4, 6) 5. w rh : wait count based on the rhc1n and rhc0n bits of the scrn register (n = 1, 3, 4, 6)
data sheet u15846ej1v0ds 51 pd70f3107a, 70f3107a(a) (b) write timing (edo dram) (2/2) clkout (output) <67> <70> <80> <73> <71> <68> <69> <68> <82> <69> <75> <74> <72> <81> <93> <76> a0 to a25 (output) <101> <81> <102> <65> <94> <95> <96> <96> <100> <99> <98> <99> <97> d0 to d15 (i/o) trpw t1 trhw t2 tdaw tcpw tb tdaw te rasn (output) lcas (output) ucas (output) we (output) oe (output) rd (output) bcyst ( output) wait (input) <66> note 2 read write d0 to d15 (i/o) write write data data data data note 1 note 1 row address column address column address notes 1. at least one clock is inserted in trpw and tcpw. 2. during on-page access from other cycles while ras is low level. remarks 1. this is the timing for the following case. wait count based on the rpc1n and rpc0n bits of the scrn register (trpw): 1 wait count based on the rhc1n and rhc0n bits of the scrn register (trhw): 1 wait count based on the dac1n and dac0n bits of the scrn register (tdaw): 1 wait count based on the cpc1n and cpc0n bits of the scrn register (tcpw): 1 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6
data sheet u15846ej1v0ds 52 pd70f3107a, 70f3107a(a) (c) dma flyby transfer timing (edo dram external i/o transfer) (1/3) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8ns wait hold time (from clkout ) <33> t hkw 0ns delay time from oe to data output <46> t drdod (1 + i)t ? 10 ns delay time from iowr to address <53> t dwra 1.5t ? 10 ns w rp = 0 (3 + w rh + w da + w)t ? 10 ns iowr low-level width <55> t wwrl w rp 1(2 + w rp + w da + w rh + w)t ? 10 ns delay time from iowr to oe <58> t dwrrd t ? 10 ns row address setup time <66> t asr 0.5t ? 10 ns row address hold time <67> t rah (0.5 + w rh )t ? 10 ns column address setup time <68> t asc 0.5t ? 10 ns column address hold time <69> t cah (2.5 + w da + w)t ? 10 ns w rp = 0 t ? 10 ns ras precharge time <70> t rp w rp 1w rp t ? 10 ns column address read time (to ras) <71> t ral (3.5 + w cp + w da + w)t ? 10 ns cas hold time <72> t csh (3 + w rh + w da + w)t ? 10 ns delay time from ras to column address <73> t rad (0.5 + w rh )t ? 10 ns delay time from ras to cas <74> t rcd (1 + w rh )t ? 10 ns w rp = 0 2t ? 10 ns cas to ras precharge time <75> t crp w rp 1(1 + w rp )t ? 10 ns ras hold time from cas precharge <76> t rhcp (4 + w cp + w da + w)t ? 10 ns w rp = 0 (3 + w rh )t ? 10 ns we setup time (to cas ) <77> t rcs w rp 1(2 + w rp + w rh )t ? 10 ns we hold time (from ras ) <78> t rrh 0ns we hold time (from cas ) <79> t rch t ? 10 ns ras pulse width off-page <80> t rasp (4 + w rh + w da + w) t ? 10 ns cas precharge time <82> t cp (1 + w cp )t ? 10 ns w rp = 0 (4 + w rh + w da + w)t ? 10 ns off-page <83> t och1 w rp 1(3 + w rp + w rh + w da + w)t ? 10 ns oe to cas hold time on-page <84> t och2 (2 + w cp + w da + w)t ? 10 ns output buffer turn-off delay time (from oe ) <92> t oez 0ns ras hold time <93> t rsh (3 + w da + w) t ? 10 ns w rp = 0 (5.5 + w rh + w da + w)t ? 10 ns read/write cycle time < 103> t rc w rp 1 (4.5 + w rp + w rh + w da + w)t ? 10 ns cas pulse width <104> t cas (2 + w da + w)t ? 10 ns w rp = 0 (3 + w rh )t ? 10 ns cas precharge time <105> t cpn w rp 1(2 + w rp + w rh )t ? 10 ns high-speed page mode cycle time < 106> t pc (3 + w cp + w da + w)t ? 10 ns
data sheet u15846ej1v0ds 53 pd70f3107a, 70f3107a(a) (c) dma flyby transfer timing (edo dram external i/o transfer) (2/3) parameter symbol conditions min. max. unit w rp = 0 (2.5 + w rh )t ? 10 ns delay time from dmaakm to cas <107> t ddacs w rp 1 (1.5 + w rp + w rh )t ? 10 ns w rp = 0 (2 + w rh )t ? 10 ns delay time from iowr to cas <108> t drdcs w rp 1(1 + w rp + w rh )t ? 10 ns output buffer turn-off delay time (from cas ) <109> t off 0ns cautions 1. at least one clock is inserted in w rp by default regardless of the setting of the rpc1n and rpc0n bits in the scrn register (n = 1, 3, 4, 6). 2. the wait signal cannot be controlled using the bcyst signal when using edo dram. remarks 1. t = t cyk 2. w: wait count based on wait 3. w da : wait count based on the dac1n and dac0n bits of the scrn register (n = 1, 3, 4, 6) 4. w cp : wait count based on the cpc1n and cpc0n bits of the scrn register (n = 1, 3, 4, 6) 5. w rp : wait count based on the rpc1n and rpc0n bits of the scrn register (n = 1, 3, 4, 6) 6. w rh : wait count based on the rhc1n and rhc0n bits of the scrn register (n = 1, 3, 4, 6) 7. i: idle state count 8. m = 0 to 3
data sheet u15846ej1v0ds 54 pd70f3107a, 70f3107a(a) (c) dma flyby transfer timing (edo dram external i/o transfer) (3/3) clkout (output) t1 trhw t2 tdaw tw tf te tcpw tb tdaw tw tf <66> <69> a0 to a23 (output) <70> <80> d0 to d15 (i/o) <71> <103> <72> <74> <104> <82> <76> <93> <78> <75> <105> <83> <106> <84> <58> <107> <77> <109> <55> <32> <32> <32> <33> <33> <92> <46> <33> <108> <79> <67> <68> <73> rasn (output) lcas (output) ucas (output) oe (output) dmaakm (output) we (output) iord (output) iowr (output) bcyst (output) wait (input) <53> te trpw note row address column address column address data data note at least one clock is inserted in trpw. remarks 1. this is the timing for the following case. wait count based on the rpc1n and rpc0n bits of the scrn register (trpw): 1 wait count based on the rhc1n and rhc0n bits of the scrn register (trhw): 1 wait count based on the dac1n and dac0n bits of the scrn register (tdaw): 1 wait count based on the cpc1n and cpc0n bits of the scrn register (tcpw): 1 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6, m = 0 to 3
data sheet u15846ej1v0ds 55 pd70f3107a, 70f3107a(a) (d) dma flyby transfer timing (external i/o edo dram transfer) (1/3) parameter symbol conditions min. max. unit wait setup time (to clkout ) <32> t swk 8ns wait hold time (from clkout ) <33> t hkw 0ns iord low-level width <41> t wrdl (2 + w rh + w da + w) t ? 10 ns iord high-level width <42> t wrdh t ? 10 ns delay time from iord to address <44> t drda (0.5 + i) t ? 10 ns row address setup time <66> t asr 0.5t ? 10 ns row address hold time <67> t rah (0.5 + w rh )t ? 10 ns column address setup time <68> t asc 0.5t ? 10 ns column address hold time <69> t cah (1.5 + w da )t ? 10 ns w rp = 0 t ? 10 ns ras precharge time <70> t rp w rp 1w rp t ? 10 ns column address read time (to ras) <71> t ral (2.5 + w cp + w da + w)t ? 10 ns cas hold time <72> t csh (2 + w rh + w da + w)t ? 10 ns delay time from ras to column address <73> t rad (0.5 + w rh ) t ? 10 ns delay time from ras to cas <74> t rcd (1 + w rh + w)t ? 10 ns w rp = 0 2t ? 10 ns cas to ras precharge time <75> t crp w rp 1(1 + w rp )t ? 10 ns ras hold time from cas precharge <76> t rhcp (4 + w cp + w da + w)t ? 10 ns ras pulse width off-page <80> t rasp (3 + w rh + w da + w)t ? 10 ns cas precharge time <82> t cp (1 + w cp + w)t ? 10 ns ras hold time <93> t rsh (2 + w da )t ? 10 ns w rp = 0 (4.5 + w rh + w da + w)t ? 10 ns read/write cycle time < 103> t rc w rp 1 (3.5 + w rp + w rh + w da + w)t ? 10 ns cas pulse width <104> t cas (1 + w da )t ? 10 ns w rp = 0 (3 + w rh + w)t ? 10 ns cas precharge time <105> t cpn w rp 1(2 + w rp + w rh + w)t ? 10 ns high-speed page mode cycle < 106> t pc (2 + w cp + w da + w)t ? 10 ns w rp = 0 (2.5 + w rh + w)t ? 10 ns delay time from dmaakm to cas <107> t ddacs w rp 1 (1.5 + w rp + w rh + w)t ? 10 ns w rp = 0 (2 + w rh + w)t ? 10 ns delay time from iord to cas <108> t drdcs w rp 1(1 + w rp + w rh + w)t ? 10 ns we read time (to ras ) <110> t rwl (3 + w da + w)t ? 10 ns we read time (to cas ) <111> t cwl (2 + w da + w)t ? 10 ns we pulse width <112> t wp (2 + w da + w)t ? 10 ns off-page <113> t wcs1 (2 + w rh + w)t ? 10 ns we setup time (to cas ) on-page <114> t wcs2 t ? 10 ns
data sheet u15846ej1v0ds 56 pd70f3107a, 70f3107a(a) (d) dma flyby transfer timing (external i/o edo dram transfer) (2/3) parameter symbol conditions min. max. unit we hold time (from cas ) <115> t wch (1 + w da )t ? 10 ns delay time from we to iord <116> t dwerd 0ns cautions 1. at least one clock is inserted in w rp by default regardless of the setting of the rpc1n and rpc0n bits in the scrn register (n = 1, 3, 4, 6). 2. at least one clock is inserted in w cp by default regardless of the setting of the cpc1n and cpc0n bits in the scrn register (n = 1, 3, 4, 6). 3. the wait signal cannot be controlled using the bcyst signal when using edo dram. remarks 1. t = t cyk 2. w: wait counts based on wait 3. w da : wait count based on the dac1n and dac0n bits of the scrn register (n = 1, 3, 4, 6) 4. w cp : wait count based on the cpc1n and cpc0n bits of the scrn register (n = 1, 3, 4, 6) 5. w rp : wait count based on the rpc1n and rpc0n bits of the scrn register (n = 1, 3, 4, 6) 6. w rh : wait count based on the rhc1n and rhc0n bits of the scrn register (n = 1, 3, 4, 6) 7. i: idle state count 8. m = 0 to 3
data sheet u15846ej1v0ds 57 pd70f3107a, 70f3107a(a) (d) dma flyby transfer timing (external i/o edo dram transfer) (3/3) clkout (output) trpw t1 trhw tw t2 tdaw te tcpw tw tb tdaw te <67> <66> <69> a0 to a23 (output) <80> d0 to d15 (i/o) <73> <71> <70> <103> <75> <72> <74> <104> <82> <93> <105> <106> <41> <108> <32> <32> <33> <33> <33> <113> <112> <111> <110> <115> <107> <32> <76> <114> <116> <42> rasn (output) lcas (output) ucas (output) oe (output) rd (output) we (output) dmaakm (output) iord (output) iowr (output) bcyst (output) wait (input) <44> row address column address column address note note <68> data data note at least one clock is inserted in trpw and tcpw. remarks 1. this is the timing for the following case. wait count based on the rpc1n and rpc0n bits of the scrn register (trpw): 1 wait count based on the rhc1n and rhc0n bits of the scrn register (trhw): 1 wait count based on the dac1n and dac0n bits of the scrn register (tdaw): 1 wait count based on the cpc1n and cpc0n bits of the scrn register (tcpw): 1 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6, m = 0 to 3
data sheet u15846ej1v0ds 58 pd70f3107a, 70f3107a(a) (e) cbr refresh timing parameter symbol conditions min. max. unit ras precharge time <70> t rp (1.5 + w rrw )t ? 10 ns ras pulse width <117> t ras (1.5 + w rcw note )t ? 10 ns cas hold time <118> t chr (0.5 + w rcw note )t ? 10 ns refrq pulse width <119> t wrfl (3 + w rrw + w rcw note )t ? 10 ns ras precharge cas hold time <120> t rpc (2.5 + w rrw )t ? 10 ns refrq active delay time (from clkout ) <121> t dkrf 213ns refrq inactive delay time (from clkout ) <122> t hkrf 213ns cas setup time <123> t csr t ? 10 ns note at least one clock is inserted in w rcw by default, regardless of the settings of the rcw0 to rcw2 bits of the rwc register. remarks 1. t = t cyk 2. w rrw : wait count based on the rrw0 and rrw1 bits of the rwc register 3. w rcw : wait count based on the rcw0 to rcw2 bits of the rwc register clkout (output) <70> trrw t1 t2 trcw trcw t3 t4 <119> <122> <117> <120> <123> <118> <120> rasn (output) refrq (output) lcas (output) ucas (output) <121> note 1 note 2 note 2 ti ti notes 1. at least one clock is inserted in trcw, regardless of the settings of the rcw0 to rcw2 bits of the rwc register. 2. idle state (ti) independent of the setting of the bcc register remarks 1. this is the timing for the following case. wait count based on the rrw0 and rrw1 bits of the rwc register (trrw): 1 wait count based on the rcw0 to rcw2 bits of the rwc register (trcw): 2 2. n = 0 to 7
data sheet u15846ej1v0ds 59 pd70f3107a, 70f3107a(a) (f) cbr self-refresh timing parameter symbol conditions min. max. unit refrq active delay time (from clkout ) <121> t dkrf 213ns refrq inactive delay time (from clkout ) <122> t hkrf 213ns cas hold time <124> t chs ? (w rcw t ? 10) ns w rp = 0 (3 + 2w srw )t ? 10 ns ras precharge time <125> t rps w rp 1(2 + 2w srw + w rpw )t ? 10 ns remarks 1. t = t cyk 2. w srw : wait count based on the srw0 to srw2 bits of the rwc register 3. w rcw : wait count based on the rcw0 to rcw2 bits of the rwc register 4. w rpw : wait count based on the rrw0 and rrw1 bits of the rwc register clkout (output) trrw trcw <122> tsrw <121> <125> <124> tsrw t1 refrq (output) rasn (output) lcas (output) ucas (output) note note at least one clock is inserted in trcw, regardless of the settings of the rcw0 to rcw2 bits of the rwc register. remarks 1. this is the timing for the following case. wait count based on the rrw0 and rrw1 bits of the rwc register (trrw): 1 wait count based on the rcw0 to rcw2 bits of the rwc register (trcw): 1 wait count based on the srw0 to srw2 bits of the rwc register (tsrw): 1 (twice the number of waits as the set value are inserted) 2. n = 1, 3, 4, 6
data sheet u15846ej1v0ds 60 pd70f3107a, 70f3107a(a) ( 8) sdram access timing (a) read timing (sdram access) (1/2) parameter symbol conditions min. max. unit address delay time (from sdclk ) <126> t dka 213ns bcyst delay time (from sdclk ) <127> t dkbc 213ns csn delay time (from sdclk ) <128> t dkcs 213ns sdras delay time (from sdclk ) <129> t dkras 213ns sdcas delay time (from sdclk ) <130> t dkcas 213ns udqm, ldqm delay time (from sdclk ) <131> t dkdqm 213ns sdcke delay time (from sdclk ) <132> t dkcke 213ns data input setup time (at sdram read, to sdclk ) <133> t sdrmk 8ns data input hold time (at sdram read, from sdclk ) <134> t hkdrm 0ns delay time from sdclk to data output <135> t dsdod (1 + i) t ? 5ns remarks 1. t = t cyk2 2. i = idle state count 3. n = 1, 3, 4, 6
data sheet u15846ej1v0ds 61 pd70f3107a, 70f3107a(a) (a) read timing (sdram access) (2/2) remarks 1. wait count based on the bcw1n and bcw0n bits of the scrn register (tbcw): 2 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6 sdclk (output) tw tact tbcw tread tlate tlate <126> bcyst (output) csn (output) sdcas (output) sdras (output) we (output) oe (output) ldqm (output) udqm (output) d0 to d15 (i/o) sdcke (output) rd (output) a10 (output) a0 to a9 (output) <126> <126> <126> <127> <128> <126> <126> <126> <126> <126> <129> <130> <131> <131> <131> <133> <134> <127> <128> <129> <130> <131> <126> data address bank address (output) <135> bank address and addresses other than a10 and a0 to a9 (output) address column address <132> <132> address address bank address row address row address
data sheet u15846ej1v0ds 62 pd70f3107a, 70f3107a(a) (b) write timing (sdram access) (1/2) parameter symbol conditions min. max. unit address delay time (from sdclk ) <126> t dka 213ns bcyst delay time (from sdclk ) <127> t dkbc 213ns csn delay time (from sdclk ) <128> t dkcs 213ns sdras delay time (from sdclk ) <129> t dkras 213ns sdcas delay time (from sdclk ) <130> t dkcas 213ns udqm, ldqm delay time (from sdclk ) <131> t dkdqm 213ns sdcke delay time (from sdclk ) <132> t dkcke 213ns we delay time (from sdclk ) <136> t dkwe 213ns data output delay time (from sdclk ) <137> t dkdt 213ns data float delay time (from sdclk ) <138> t hzkdt 213ns remark n = 1, 3, 4, 6
data sheet u15846ej1v0ds 63 pd70f3107a, 70f3107a(a) (b) write timing (sdram access) (2/2) tw tact tbcw twr1 twr2 twr3 <126> <126> <126> <126> <127> <128> <126> <126> <126> <126> <126> <129> <130> <136> <131> <131> <131> <137> <138> <127> <128> <129> <130> <136> <131> <126> <132> <132> sdclk (output) bcyst (output) csn (output) sdcas (output) sdras (output) we (output) oe (output) ldqm (output) udqm (output) d0 to d15 (i/o) sdcke (output) rd (output) a10 (output) a0 to a9 (output) bank address (output) bank address and addresses other than a10 and a0 to a9 (output) data address address address address column address bank address row address row address remarks 1. wait count based on the bcw1n and bcw0n bits of the scrn register (tbcw): 2 2. broken lines indicate high impedance. 3. n = 1, 3, 4, 6
data sheet u15846ej1v0ds 64 pd70f3107a, 70f3107a(a) (9) dmac timing parameter symbol conditions min. max. unit dmarqn setup time (to clkout ) <139> t sdrk 8ns <140> t hkdr1 after inactive (from clkout )3 ns dmarqn hold time <141> t hkdr2 until dmaakn ns second dma request disable timing in single transfer <142> t akdr 3t ns dmaakn output delay time (from clkout ) <143> t dkda 213ns dmaakn output hold time (from clkout ) <144> t hkda 213ns tcn output delay time (from clkout ) <145> t hktc 213ns tcn output hold time (from clkout ) <146> t hktc 213ns remarks 1. t = t cyk 2. n = 0 to 3 remarks 1. in 2-cycle transfer, the tcn signal is output in the write cycle. 2. n = 0 to 3 clkout (output) <141> <143> <144> <145> <139> dmaakn (output) dmarqn (input) tcn (output) <142> <140> <146>
data sheet u15846ej1v0ds 65 pd70f3107a, 70f3107a(a) (10) bus hold timing (1/2) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) <147> t shrk 8ns hldrq hold time (from clkout ) <148> t hkhr 3ns delay time from clkout to hldak <149> t dkha 213ns hldrq high-level width <150> t whqh t + 3ns hldak low-level width <151> t whal t ? 11 ns delay time from hldak to bus float <152> t dkcf 0ns delay time from hldak to bus output <153> t dhac 213ns delay time from hldrq to hldak <154> t dhqha1 2t ns delay time from hldrq to hldak <155> t dhqha2 t 2t + 10 ns remark t = t cyk
data sheet u15846ej1v0ds 66 pd70f3107a, 70f3107a(a) (10) bus hold timing (2/2) clkout (output) ti d0 to d15 (i/o) <147> th th th ti t1 <148> <148> <147> <154> <149> <151> <155> <150> <149> <152> <153> a0 to a25 (output) address data hldrq (input) hldak (output) csn/rasn (output) bcyst (output) rd (output) we (output) lcas (output) ucas (output) wait (input) <147> undefined remarks 1. broken lines indicate high impedance. 2. n = 0 to 7
data sheet u15846ej1v0ds 67 pd70f3107a, 70f3107a(a) (11) interrupt timing parameter symbol conditions min. max. unit nmi high-level width <156> t wnih 500 ns nmi low-level width <157> t wnil 500 ns intp0nm high-level width <158> t wit0h 3t + 500 ns intp0nm low-level width <159> t wit0l 3t + 500 ns intp1nm high-level width <160> t wit1h 500 ns intp1nm low-level width <161> t wit1l 500 ns remarks 1. intp0nm: n = 0 to 3, m = 0, 1 intp1nm: n = 0 to 3, m = 0 to 3 2. t = t cyk <156> <157> nmi (input) <158> <159> intp0nm (input) <160> <161> intp1nm (input) remark intp0nm: n = 0 to 3, m = 0, 1 intp1nm: n = 0 to 3, m = 0 to 3 (12) rpu timing parameter symbol conditions min. max. unit ti0n0 high-level width <162> t wtih 3t + 500 ns ti0n0 low-level width <163> t wtil 3t + 500 ns remarks 1. n = 0 to 3 2. t = t cyk remark n = 0 to 3 <162> <163> ti0n0 (input)
data sheet u15846ej1v0ds 68 pd70f3107a, 70f3107a(a) (13) csi0 to csi2 timing (1/3) (a) master mode parameter symbol conditions min. max. unit sckn cycle < 164> t cysk1 output 320 ns sckn high-level width <165> t wsk1h output 0.5t cysk1 ? 20 ns sckn low-level width <166> t wsk1l output 0.5t cysk1 ? 20 ns sin setup time (to sckn )30ns sin setup time (to sckn ) <167> t ssisk 30 ns sin hold time (from sckn )30ns sin hold time (from sckn ) <168> t hsksi 30 ns son output delay time (from sckn )30ns son output delay time (from sckn ) <169> t dskso 30 ns son output hold time (from sckn )0.5t cysk1 ? 5ns son output hold time (from sckn ) <170> t hskso 0.5t cysk1 ? 5ns remark n = 0 to 2 (b) slave mode parameter symbol conditions min. max. unit sckn cycle < 164> t cysk1 input 200 ns sckn high-level width <165> t wsk1h input 90 ns sckn low-level width <166> t wsk1l input 90 ns sin setup time (to sckn )50ns sin setup time (to sckn ) <167> t ssisk 50 ns sin hold time (from sckn )50ns sin hold time (from sckn ) <168> t hsksi 50 ns son output delay time (from sckn )50ns son output delay time (from sckn ) <169> t dskso 50 ns son output hold time (from sckn )t wsk1h ns son output hold time (from sckn ) <170> t hskso t wsk1h ns remark n = 0 to 2
data sheet u15846ej1v0ds 69 pd70f3107a, 70f3107a(a) (13) csi0 to csi2 timing (2/3) (c) timing when ckpn, dapn bits of csicn register = 00 <164> <166> <165> <167> <168> <169> <170> sin (input) son (output) sckn (i/o) input data output data remarks 1. broken lines indicate high impedance. 2. n = 0 to 2 (d) timing when ckpn, dapn bits of csicn register = 01 remarks 1. broken lines indicate high impedance. 2. n = 0 to 2 <167> <168> <170> sin (input) son (output) input data output data <164> <166> <165> sckn (i/o) <169>
data sheet u15846ej1v0ds 70 pd70f3107a, 70f3107a(a) (13) csi0 to csi2 timing (3/3) (e) timing when ckpn, dapn bits of csicn register = 10 remarks 1. broken lines indicate high impedance. 2. n = 0 to 2 (f) timing when ckpn, dapn bits of csicn register = 11 remarks 1. broken lines indicate high impedance. 2. n = 0 to 2 <164> <166> <165> <167> <168> <169> <170> input data output data sckn (i/o) son (output) sin (input) <167> <168> <170> sin (input) son (output) input data output data <164> <166> <165> sckn (i/o) <169>
data sheet u15846ej1v0ds 71 pd70f3107a, 70f3107a(a) a/d converter characteristics (t a = ? ? ? ? 40 to +85 c, v dd = av dd = 3.0 to 3.6 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution ? 10 bit overall error note 1 ? 0.49 %fsr quantization error ? 1/2 %fsr conversion time t conv 510 s sampling time t samp conversion clock note 2 /6 ns zero-scale error note 1 ? 0.49 %fsr full-scale error note 3 ? 0.49 %fsr integral linearity error note 3 ? 4lsb differential linearity error note 3 ? 4lsb analog input voltage v wasn ? 0.3 av ref + 0.3 v av ref input voltage av ref av ref = av dd 3.0 3.6 v av dd supply current ai dd 10 ma notes 1. excluding quantization error ( 0.05 %fsr) 2. conversion clock is the number of clocks set by the adm1 resister. 3. excluding quantization error ( 0.5 lsb) remark lsb: least significant bit fsr: full scale range % fsr is the ratio to the full-scale value.
data sheet u15846ej1v0ds 72 pd70f3107a, 70f3107a(a) 4.2 flash memory programming mode basic characteristics (t a = 10 to 40 c (during rewrite), t a = ? ? ? ? 40 to +85 c (except during rewrite), v dd = av dd = 3.0 to 3.6 v, v ss = av ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit operating frequency f xx 450mhz v pp1 during flash memory programming 7.5 7.8 8.1 v v ppl v pp low-level detection ? 0.5 0.2v dd v v ppm v pp , v dd level detection 0.65v dd v dd + 0.3 v v pp supply voltage v pph v pp high-voltage level detection 7.5 7.8 8.1 v v dd supply current i dd v pp = v pp1 4.8fxx + 45 ma v pp supply current i pp v pp = 7.8 v 100 ma step erase time t er note 1 0.398 0.4 0.402 s overall erase time per area t era when the step erase time = 0.4 s note 2 40 s/area write-back time t wb note 3 0.99 1 1.01 ms number of write-backs per write-back command c wb when the write-back time = 1 ms note 4 300 count/write -back command number of erase/write-backs c erwb 16 count step writing time t wt note 5 18 20 22 s overall writing time per word t wtw when the step writing time = 20 s (1 word = 4 bytes) note 6 20 200 s/word notes 1. the recommended setting value of the step erase time is 0.4 s. 2. the prewrite time prior to erasure and the erase verify time (write-back time) are not included. 3. the recommended setting value of the write-back time is 1 ms. 4. write-back is executed once by the issuance of the write-back command. therefore, the retry count must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step writing time is 20 s. 6. 100 s is added to the actual writing time per word. the internal verify time during and after the writing is not included. remarks 1. when the pg-fp3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. do not change the settings otherwise specified. 2. area 0 = 00000h to 1ffffh, area 1 = 20000h to 3ffffh
data sheet u15846ej1v0ds 73 pd70f3107a, 70f3107a(a) basic characteristics (t a = 10 to 40 c (during rewrite), t a = ? ? ? ? 40 to +85 c (except during rewrite), v dd = av dd = 3.0 to 3.6 v, v ss = av ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit note 2 20 number of rewrites per area c erwr 1 erase + 1 write after erase = 1 rewrite note 1 note 3 100 count/area notes 1. when writing initially to shipped products, it is counted as one rewrite for both ?erase to write? and ?write only?. example (p: write, e: erase) shipped product ???? p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites 2. lqfp package: lot number 0124pxxxx or earlier fbga package: lot number 0123pxxxx or earlier 3. lqfp package: lot number 0125pxxxx or later fbga package: lot number 0124pxxxx or later remarks 1. when the pg-fp3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. do not change the settings otherwise specified. 2. area 0 = 00000h to 1ffffh, area 1 = 20000h to 3ffffh 3. 01 indicates the year of manufacture and 23, 24, 25 indicate the week of manufacture. the products that are guaranteed for 100 rewrites are as follows. lqfp package: products manufactured in 25th week or later (25, 26, 27?) fbga package: products manufactured in 24th week or later (24, 25, 26?)
data sheet u15846ej1v0ds 74 pd70f3107a, 70f3107a(a) serial write operation characteristics parameter symbol conditions min. typ. max. unit v dd to v pp set time <171> t drpsr 10 s v pp to reset set time <172> t psrrf 1 s reset to v pp count start time <173> t rfof v pp = 7.8 v 10t + 1500 ns count execution time <174> t count 15 ms v pp counter high-level width <175> t ch 1 s v pp counter low-level width <176> t cl 1 s v pp counter rise time <177> t r 1 s v pp counter fall time <178> t f 1 s v pp to v dd reset time <179> t pfdr 10 s remark t = t cyk <171> <173> <176> <175> <174> <178> <177> v dd v dd v dd v pph 0 v 0 v 0 v v dd v pp reset (input) <172> <179>
data sheet u15846ej1v0ds 75 pd70f3107a, 70f3107a(a) 5. package drawing 108 73 136 109 144 72 37 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 0.2 b 20.0 0.2 c 20.0 0.2 d f 1.25 22.0 0.2 s144gj-50-uen s 1.5 0.1 k 1.0 0.2 l 0.5 0.2 r3 + 4 ? 3 g 1.25 h 0.22 0.05 i 0.08 j 0.5 (t.p.) m 0.17 n 0.08 p 1.4 q 0.10 0.05 + 0.03 ? 0.07 each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. s s m detail of lead end i j f g h q r p k m l n cd s a b
data sheet u15846ej1v0ds 76 pd70f3107a, 70f3107a(a) 161-pin plastic fbga (13x13) item millimeters d e 13.00 0.10 13.00 0.10 w0.20 e x0.08 y0.10 a1.48 0.10 a1 0.35 0.06 a2 1.13 0.80 index mark a a2 a1 ze zd y1 0.20 zd 1.30 ze 1.30 b 0.50 + 0.05 ? 0.10 p161f1-80-en4-1 a b c d e f g h j k l m n p 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b s y1 e s y s s w a s w b s b x ab m e d
data sheet u15846ej1v0ds 77 pd70f3107a, 70f3107a(a) 6. recommended soldering conditions the pd70f3107a and 70f3107a(a) should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 6-1. surface mounting type soldering conditions (1) pd70f3107agj-uen: 144-pin plastic lqfp (fine pitch) (20 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 to 72 hours) ir35-103-2 vps package peak temperature: 215 c, time: 25 to 40 seconds (at 200 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 to 72 hours) vp15-103-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? (2) pd70f3107af1-en4: 161-pin plastic fbga (13 13) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) ir35-107-2 vps package peak temperature: 215 c, time: 25 to 40 seconds (at 200 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) vp15-107-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remark the soldering conditions for the following product is undetermined. ? pd70f3107agj(a)-uen: 144-pin plastic lqfp (fine pitch) (20 20)
data sheet u15846ej1v0ds 78 pd70f3107a, 70f3107a(a) appendix notes on target system design the following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. design your system making allowances for conditions such as the form of parts mounted on the target system as shown below. appendix-1. 144-pin plastic lqfp (fine pitch) (20 20) side view target system nqpack144sd yqpack144sd 206.26 mm note in-circuit emulator option board conversion connector ie-703107-mc-em1 in-circuit emulator ie-v850e-mc-a yqguide note yqsocket144sdn (sold separately) can be inserted here to adjust the height (height: 3.2 mm). top view target system yqpack144sd, nqpack144sd, yqguide ie-703107-mc-em1 ie-v850e-mc-a connection condition diagram 13.3 mm 27.205 mm 21.58 mm 17.99 mm 75 mm 31.84 mm target system nqpack144sd yqpack144sd ie-703107-mc-em1 connect to ie-v850e-mc-a. yqguide remark the connector for the 161-pin plastic fbga package is under development.
data sheet u15846ej1v0ds 79 pd70f3107a, 70f3107a(a) [memo]
data sheet u15846ej1v0ds 80 pd70f3107a, 70f3107a(a) notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. related document: pd703103a, 703105a, 703106a, 703106a(a), 703107a, 703107a(a) data sheet (u15578e) the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. v850e/ma1 and v850 series are trademarks of nec corporation.
data sheet u15846ej1v0ds 81 pd70f3107a, 70f3107a(a) regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.12 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ? branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (france) s.a. v lizy-villacoublay, france tel: 01-3067-58-00 fax: 01-3067-58-99 nec electronics (france) s.a. representaci?n en espa?a madrid, spain tel: 091-504-27-87 fax: 091-504-28-60
pd70f3107a, 70f3107a(a) m8e 00. 4 the information in this document is current as of november, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": com puters, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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